Methods of making power semiconductor devices with thick bottom oxide layer

• US 8,143,124 B2
• Filed: 02/15/2008
• Issued: 03/27/2012
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sapp, Steven P., Wilson, Peter H., Sani, Babak S., Losee, Becky, Herrick, Robert, Murphy, James J., Madson, Gordon K., Challa, Ashok, Marchant, Bruce D., Elbanhawy, Alan, Kocon, Christopher B., Probst, Dean E., Woolsey, Debra S.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US12/032,599
• Publication Number:
  US 20080138953A1
• Time in Patent Office: 1,502 Days
• Field of Search: 438/270
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.

Claims

1. A method of of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate;

etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench.

3. The method of claim 1 further comprising masking the charge control trench so that the charge control trench remains substantially filled with oxide.

2. A method of of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a layer of pad oxide on the substrate;

depositing a thin layer of silicon nitride on the pad oxide;

performing an anisotropic etch to remove silicon nitride from horizontal surfaces leaving silicon nitride on active trench sidewalls;

depositing oxide on horizontal surfaces including the bottom of the active trench using a sub-atmospheric chemical vapor deposition process;

removing a sandwich layer of oxide-nitride-oxide from active trench sidewalls by an etch process;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench.

4. A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a substantially flat layer of oxide having a target thickness at the bottom of the active trench;

lining the sidewalls of the active trench with an oxide material;

depositing a first conductive layer over the thick oxide layer on the bottom of the active trench;

depositing an inter-electrode dielectric material over the first conductive layer;

depositing a second conductive layer over the inter-electrode dielectric material; and

forming source regions having the first conductivity type in the well region adjacent the active trench.

5. A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a substantially flat layer of oxide having a target thickness at the bottom of the active trench;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench;

depositing in the charge control trench a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material;

wherein the thickness of the plurality of conductive layers inside the charge control trench vary.

6. A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom comprising:

forming a drift region of a first conductivity type;

forming a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

forming an active trench extending through the well region and into the drift region;

forming a charge control trench extending deeper into the drift region than the active trench;

forming a substantially flat layer of oxide having a target thickness at the bottom of the active trench;

forming an electrode in the active trench; and

forming source regions having the first conductivity type in the well region adjacent the active trench;

depositing in the charge control trench a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material;

wherein the thickness of a first conductive layer that is deeper inside the charge control trench is smaller than the thickness of a second conductive layer that is disposed above the first conductive layer.