Structure and method for forming a salicide on the gate electrode of a trench-gate FET

• US 8,143,125 B2
• Filed: 03/27/2009
• Issued: 03/27/2012
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Purtell, Robert J., Murphy, James J.
• Primary Examiner(s): Sandvik, Benjamin
• Assistant Examiner(s): KHAN, FARID H
• Application Number:
  US12/412,803
• Publication Number:
  US 20100244126A1
• Time in Patent Office: 1,096 Days
• Field of Search: 438/259, 438/268, 438/270, 438/272, 438/589, 257/330, 257/332, 257/E21.41, 257/E21.419, 257/E21.428, 257/E21.429, 257/E21.655, 257/E29.201, 257/E29.257, 257/E29.6, 257/E29.262, 257/E29.274
• US Class Current: 438/270
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.

Claims

1. A method of forming a trench-gate FET structure, the method comprising:

forming a plurality of trenches extending into a semiconductor region;

forming a gate dielectric layer extending continuously along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches;

forming a gate electrode inside each trench;

forming well regions of a second conductivity type ill the semiconductor region;

forming source regions of the first conductivity type in upper portions of the well regions;

after forming the source regions, forming a concave-shaped salicide layer comprising at least one of cobalt or nickel over the gate electrode inside each trench abutting portions of the gate dielectric layer, wherein the gate dielectric layer prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between the adjacent trenches;

forming a dielectric layer over the concave-shaped salicide layer in each trench; and

forming an interconnect layer over the dielectric layer, the dielectric layer isolating the interconnect layer from the concave-shaped salicide layer and portions of the gate dielectric layer isolating the interconnect layer from the mesa surfaces between the adjacent trenches.

2. The method of claim 1, wherein the concave-shaped salicide layer comprises at least one of cobalt, nickel, or molybdenum.

3. The method of claim 1, wherein forming the well regions comprises performing a thermal process substantially without oxygen to minimize oxide formation over the gate electrode in each trench.

4. The method of claim 1, wherein forming the source regions comprises performing a thermal process substantially without oxygen to minimize oxide formation over the gate electrode in each trench.

5. The method of claim 1, further comprising:

performing a wet clean process without HF to minimize removal of exposed portions of the gate dielectric layer.

6. The method of claim 1, wherein the source regions are formed adjacent to the opposing sidewalls of each trench, and the concave-shaped salicide layer in each trench overlaps bottom portions of the adjacent source regions along a depth of the plurality of trenches.

7. The method of claim 1, wherein forming the concave-shaped salicide layer comprises:

forming a metal layer extending over exposed portions of the gate dielectric layer and over the gate electrode in each trench;

performing a thermal process such that portions of the metal layer extending over the gate electrode in each trench react to form the concave-shaped salicide layer; and

removing unreacted portions of the metal layer.

8. The method of claim 1, further comprising:

forming a shield electrode in each trench under the gate electrode; and

forming an inter-electrode dielectric in each trench extending between the shield electrode and the gate electrode.

9. A method of forming a trench-gate FET structure, the method comprising:

forming a trench extending into the semiconductor region;

forming a gate dielectric layer along sidewalls of the trench and extending continuously over mesa surfaces of the semiconductor region adjacent to the trench;

forming a gate electrode inside the trench;

performing a first implant of dopants of the first conductivity type into the semiconductor region;

performing a second implant of dopants of a second conductivity type into the semiconductor region;

performing one or more thermal processes to thereby form a source region corresponding to the first implant and a well region corresponding to the second implant, the one or more thermal processes being performed substantially without oxygen to minimize oxide formation over the gate electrode;

after performing the thermal process, forming a concave-shaped salicide layer comprising at least one of cobalt or nickel over the gate electrode abutting portions of the gate dielectric layer, wherein the gate dielectric layer prevents formation of the salicide layer along the mesa surfaces of the semiconductor region;

forming a dielectric layer over the concave-shaped salicide layer in each trench; and

forming an interconnect layer over the dielectric layer, the dielectric layer isolating the interconnect layer from the concave-shaped salicide layer and portions of the gate dielectric layer isolating the interconnect layer from the source regions between adjacent trenches.

10. The method of claim 9, wherein the concave-shaped salicide layer comprises at least one of cobalt, nickel. or molybdenum.

11. The method of claim 9, wherein the concave-shaped salicide layer overlaps a bottom portion of the source region along a depth of the trench.

12. The method of claim 9, further comprising:

performing a wet clean process without HF to minimize removal of exposed portions of the gate dielectric layer.

13. The method of claim 9, wherein forming the concave-shaped salicide layer comprises:

forming a metal layer extending over exposed portions of the gate dielectric layer and the gate electrode;

performing a second thermal process such that portions of the metal layer extending over the gate electrode react to form a mono-silicide;

removing unreacted portions of the metal layer; and

performing a third thermal process such that the mono-silicide reacts to form the concave-shaped salicide layer.

14. A trench-gate FET structure comprising:

trenches extending into a semiconductor region, wherein portions of the semiconductor region extending between adjacent trenches form mesa surfaces;

a gate dielectric layer extending continuously along sidewalls of each trench and over the mesa surfaces between the trenches;

a gate electrode inside each trench;

a concave-shaped salicide layer comprising at least one of cobalt or nickel extending over the gate electrode inside each trench and abutting portions of the gate dielectric layer;

a dielectric layer over the concave-shaped salicide layer in each trench; and

an interconnect layer over the dielectric layer and over portions of the gate dielectric layer extending over the mesa surfaces between the adjacent trenches.

15. The trench-gate FET structure of claim 14, wherein the concave-shaped salicide layer comprises at least one of cobalt, nickel, or molybdenum.

16. The trench-gate FET structure of claim 14, further comprising:

well regions of a second conductivity type in the semiconductor region and

source regions of a first conductivity type in upper portions of the well regions, wherein the well regions and the source regions are adjacent to the sidewalls of each trench, and wherein the concave-shaped salicide layer in each trench overlaps bottom portions of adjacent source regions along a depth of the trenches.

17. The trench-gate FET structure of claim 14, wherein portions of the gate dielectric layer extending over the mesa surfaces isolate the interconnect layer from the semiconductor region and the dielectric layer isolates the interconnect layer from the concave-shaped salicide layer.

18. The trench-gate FET structure of claim 14, wherein a top surface of the concave-shaped salicide layer in each trench is recessed relative to adjacent mesa surfaces.

19. The trench-gate FET structure of claim 14, further comprising:

a shield electrode in each trench under the gate electrode; and

an inter-electrode dielectric in each trench extending between the shield electrode and the gate electrode.