Method for forming a vertical MOS transistor

• US 8,143,126 B2
• Filed: 05/10/2010
• Issued: 03/27/2012
• Est. Priority Date: 05/10/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Qin, Ganming, de Fresart, Edouard D., Ku, Pon Sung, Chen, Jingjing
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US12/777,066
• Publication Number:
  US 20110275187A1
• Time in Patent Office: 687 Days
• Field of Search: 438268-270, 438/589, 257/E21.417
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.

Claims

1. A method of forming a vertical MOS transistor using a semiconductor layer, comprising:

etching an opening in the semiconductor layer;

forming a gate dielectric in the opening that has a vertical portion that extends to a top surface of the semiconductor layer;

forming a gate in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric;

performing an implant to form a source region at the top surface of the semiconductor layer while the overhang portion is present; and

forming a third insulating layer in the opening in the semiconductor layer having the first etch characteristic; and

removing the third insulating layer using an etchant that laterally etches the first insulating layer to leave an undercut region between the first semiconductor layer and the second insulating layer prior to forming the gate dielectric.

2. The method of claim 1, further comprising:

forming a first insulating layer on the semiconductor layer prior to the step of etching, wherein the first insulating layer has a first etch characteristic; and

forming a second insulating layer on the first insulating layer prior to the step of etching, wherein the step of etching forms an opening in the first insulating layer and the second insulating layer aligned to the opening in the semiconductor layer.

3. The method of claim 1, wherein the step of forming the gate comprises depositing a first gate material layer in the first opening and in the undercut.

4. The method of claim 3 wherein the step of forming the gate further comprises etching back the first gate material layer while leaving at least a first portion of the first gate material layer that was in the opening in the semiconductor layer and a second portion of the first gate material in the undercut, wherein the second portion of the first gate material layer comprises at least a portion of the overhang portion.

5. The method of claim 4, further comprising removing the second insulating layer after the step of etching back the first gate material layer.

6. The method of claim 4, wherein the step of forming the gate further comprises:

depositing a second gate material layer over the first gate material layer after the step of etching back the first gate material layer; and

etching back the second layer of gate material.

7. The method of claim 6, further comprising removing the first insulating layer after the step of etching back the second layer of gate material.

8. The method of claim 4, further comprising:

performing an implant to convert a top portion of the semiconductor layer to a first conductivity type, wherein the source is a second conductivity type.

9. The method of claim 8, wherein:

the step of performing the implant to convert is further characterized by the implant being to a first depth in the semiconductor layer; and

the step of etching the opening in the semiconductor layer is to a second depth in the semiconductor layer, wherein the second depth is greater than the first depth.

10. The method of claim 1, wherein the overhang portion extends over a portion of a top surface of the semiconductor layer.

11. The method of claim 1 wherein the step of forming the gate comprises:

depositing a layer of gate material over the semiconductor layer and in the opening; and

patterning the layer of gate material to leave portions of the layer of gate material comprising the major portion of the gate and the lateral portion of the gate.

12. A method of forming a vertical MOS transistor using a semiconductor layer, comprising:

etching an opening in the semiconductor layer;

forming a gate dielectric in the opening that has a vertical portion that extends to a top surface of the semiconductor layer;

forming a gate in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric;

performing an implant to form a source region at the top surface of the semiconductor layer while the overhang portion is present;

forming a first oxide layer on the semiconductor layer prior to the step of etching;

forming a nitride layer on the first oxide layer, wherein the step of etching forms an opening in the first oxide layer and the nitride layer aligned to the opening in the semiconductor layer;

growing a second oxide layer in the opening in the semiconductor layer; and

removing the second oxide layer using an etchant that laterally etches the first oxide layer to leave an undercut region between the first oxide layer and the nitride layer prior to forming the gate dielectric; and

wherein the step of forming the gate comprises depositing polysilicon in the opening in the semiconductor layer and in the undercut.

13. A method of forming a vertical MOS transistor using a semiconductor layer, comprising:

forming a oxide layer on the semiconductor layer;

forming a nitride layer on the oxide layer;

etching an opening in the semiconductor layer, the first insulating layer, and the second insulating layer;

growing a second oxide layer in the opening in the semiconductor layer;

removing the second oxide layer using an etchant that laterally etches the first oxide layer to leave an undercut region between the semiconductor layer and the nitride layer;

forming a gate dielectric in the opening;

depositing gate material in the opening, in the undercut region, and over the nitride layer whereby the gate material is present in a region of the undercut region;

etching back the gate material to leave a first portion of the gate material in the opening and a second portion of the gate material in the region of the undercut region; and

performing an implant to form a source region at the top surface of the semiconductor layer using the second portion of the gate material as a mask.

14. The method of claim 13 wherein the step of etching back comprises:

performing an initial etch at a first rate; and

performing a subsequent etch at a second rate slower than the first rate.

15. The method of claim 14, wherein at least 90 percent of the step of etching back is performed by the initial etch.

16. The method of claim 13, wherein the step of depositing gate material comprises depositing polysilicon which is followed by performing an etch back which is followed by a deposition of polysilicon.

17. The method of claim 13 further comprising implanting into the semiconductor to a depth in the semiconductor layer less than a depth of the opening in the semiconductor layer of a conductivity type opposite to that of the source region.

18. A method of forming a vertical MOS transistor using a semiconductor layer, comprising:

etching an opening in the semiconductor layer;

forming a gate dielectric in the opening;

forming a gate having a major portion in the opening and an overhang portion that is at a higher level than a top surface of the semiconductor layer and that extends laterally over at least a portion of the gate dielectric; and

performing an implant to form a source region at the top surface of the semiconductor layer using the overhang portion as a mask that reduces a depth of the implant into the gate dielectric under the overhang portion,

wherein the overhang portion is formed by filling with polysilicon an undercut of an oxide layer formed on a top surface of the semiconductor layer.