Semiconductor nanowire and its manufacturing method

• US 8,143,144 B2
• Filed: 06/04/2008
• Issued: 03/27/2012
• Est. Priority Date: 06/06/2007
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kawashima, Takahiro, Saitoh, Tohru
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US12/451,898
• Publication Number:
  US 20100133509A1
• Time in Patent Office: 1,392 Days
• Field of Search: 438/478, 438/479, 438/493, 438/962, 977/890, 977/891, 977/892, 257/12, 257/14, 257/15, 257/20, 257/24
• US Class Current: 438/478
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: C30B 11/12 Vaporous components, e.g. vapour-liquid-solid-growth
• CPC Class Codes: C30B 25/00 Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: C30B 29/40 AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
• CPC Class Codes: C30B 29/60 characterised by shape
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/02653 Vapour-liquid-solid growth
• CPC Class Codes: H01L 21/02656 Special treatments
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: Y10S 438/962 Quantum dots and lines

Abstract

A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

Claims

1. A method for fabricating a semiconductor nanowire that has first and second regions, the method comprising:

putting a catalyst particle on a substrate;

growing the first region from the catalyst particle with a vapor-liquid-solid phase (VLS) grower;

forming a protective coating on a sidewall of the first region; and

growing the second region extending from the first region with the VLS grower.

2. The method of claim 1, wherein a conductivity type of the first region is one of N and P types and a conductivity type of the second region is an other of N and P types.

3. The method of claim 1, wherein a conductivity type of the first region is the same as a conductivity type of the second region, and wherein an electrical conductivity of the second region is lower than an electrical conductivity of the first region.

4. The method of claim 1, wherein the catalyst particle comprises one of a metal and an alloy of a metal and further comprises a semiconductor.

5. The method of claim 1, wherein the second region comprises a semiconductor material doped with a dopant element.

6. The method of claim 5, wherein at a growth temperature of the second region, a solid solubility of the dopant element with respect to the catalyst particle is at most 1×

10¹⁹ atoms/cm³.

7. The method of claim 6, wherein the first and second regions comprise a semiconductor material that includes at least one element selected from a group consisting of Si, Ge and C.

8. The method of claim 5, wherein the dopant element comprises at least one element selected from a group consisting of B, P, As and Sb.

9. The method of claim 1, wherein, when growing the second region, a constituent element of the second region diffuses through the protective coating and does not diffuse to the first region.

10. The method of claim 9, wherein the protective coating includes at least one film selected from a group consisting of a silicon dioxide film, a silicon oxynitride film and a silicon nitride film.

11. The method of claim 1, wherein a bandgap of the first region is different from a bandgap of the second region.

12. The method of claim 11, wherein the second region comprises at least two different elements and wherein at a growth temperature of the second region, a solid solubility of at least one of the at least two different elements of the second region with respect to the catalyst particle is at most 1×

10¹⁹ atoms/cm³.

13. The method of claim 1, wherein the protective coating is formed by thermally oxidizing the first region.

14. A semiconductor nanowire comprising:

a first region including a dopant in a concentration of at least 1×

10¹⁹ atoms/cm³;

a second region, arranged continuously with the first region in a longitudinal direction thereof and including one of a first dopant in a concentration of at most 1×

10¹⁸ atoms/cm³ and no dopant; and

a third region arranged continuously with the second region in the longitudinal direction thereof and including a second dopant in a concentration of at least 1×

10¹⁹ atoms/cm³.

15. A semiconductor device with the semiconductor nanowire of claim 14, comprising:

a source electrode connected to the first region of the semiconductor nanowire;

a drain electrode connected to the third region of the semiconductor nanowire;

a gate electrode facing the second region of the semiconductor nanowire; and

a gate insulating film arranged between the second region and the gate electrode.

16. A semiconductor nanowire, comprising:

a first region including a dopant;

a second region having a lower dopant concentration than the first region and arranged continuously with the first region in a longitudinal direction thereof;

a third region, which has having a higher dopant concentration than the second region and arranged continuously with the second region in the longitudinal direction thereof;

a first sidewall arranged on a side surface of the first region and including a first polycrystalline material; and

a second sidewall arranged on a side surface of the third region and including a second polycrystalline material,

wherein the first sidewall and the second sidewall are not arranged on a side surface of the second region.

17. The semiconductor nanowire of claim 16, wherein a thickness of the first sidewall and a thickness of the second sidewall one of increase and decrease in a direction extending toward the second region.

18. A semiconductor device with the semiconductor nanowire of claim 16, the device comprising:

a source electrode connected to the first region of the semiconductor nanowire;

a drain electrode connected to the third region of the semiconductor nanowire;

a gate electrode facing the second region of the semiconductor nanowire; and

a gate insulating film arranged between the second region and the gate electrode.