Thin film transistors having multi-layer channel

• US 8,143,678 B2
• Filed: 11/30/2007
• Issued: 03/27/2012
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-Chul, Kim, Sun-Il, Park, Young-soo
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US11/987,499
• Publication Number:
  US 20080191204A1
• Time in Patent Office: 1,579 Days
• Field of Search: 257/404, 257/E27.112
• US Class Current: 257/404
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor may include: a gate insulting layer; a gate electrode formed on the gate insulating layer; a channel layer formed on the gate insulating layer; and source and drain electrodes that contact the channel layer. The channel layer may have a double-layer structure, including upper and lower layers. The upper layer may have a carrier concentration lower than the lower layer. A method of manufacturing a transistor may include: forming a channel layer on a substrate; forming source and drain electrodes on the substrate; forming a gate insulating layer on the substrate; and forming a gate electrode on the gate insulating layer above the channel layer. A method of manufacturing a transistor may include: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate; forming a channel layer on the gate insulating layer; and forming source and drain electrodes on the gate insulating layer.

Claims

1. A thin film transistor, comprising:

a gate insulating layer;

a gate electrode formed on a first side of the gate insulating layer;

a channel layer formed of a ZnO based material on a second side of the gate insulating layer;

a source electrode that contacts a first portion of the channel layer; and

a drain electrode that contacts a second portion of the channel layer;

wherein the channel layer has a double-layer structure, including an uppermost layer and a lower layer, the lower layer being disposed between the uppermost layer and the gate insulating layer,

wherein a thickness of the uppermost layer is greater than or equal to 10 nm and less than or equal to 100 nm,

wherein the uppermost layer is doped with a carrier acceptor and the lower layer is not doped with the carrier acceptor, and the uppermost layer has a lower carrier concentration than the lower layer, so that an electrical resistance of the uppermost layer is higher than the electrical resistance of the lower layer,

wherein the carrier acceptor comprises Cu, and

wherein a Cu content of the uppermost layer is 29-44 atomic %.

2. The transistor of claim 1, wherein the channel layer is formed of a(In₂O₃).b(Ga₂O₃).c(ZnO), and

wherein a, b, and c are real numbers such that a≧

0, b≧

0, and c>

0.

3. The transistor of claim 1, wherein the carrier acceptor further comprises one or more of Ag, Li, Na, K, Mg, Ca, Be, Au, Rg, Ni, Co, Rh, Pd, Ir, Pt, V, Nb, Ta, and N.

4. The transistor of claim 1, wherein the gate electrode is disposed under the channel layer.

5. The transistor of claim 1, wherein the channel layer is formed of Ga—

In—

Zn—

O material.

6. The transistor of claim 1, wherein the channel layer is formed of a(In₂O₃).b(Ga₂O₃).c(ZnO), and

wherein a, b, and c are real numbers such that a≧

1, b≧

1, and 1≧

c>

0.

7. The transistor of claim 1, wherein a thickness of the channel layer is greater than or equal to 30 nm and less than or equal to 200 nm.