Vented die and package

• US 8,143,719 B2
• Filed: 06/05/2008
• Issued: 03/27/2012
• Est. Priority Date: 06/07/2007
• Status: Expired due to Fees

• Current Assignee: Utac Headquarters Pte. Ltd (UTAC Holdings Ltd.)
• Original Assignee: United Test and Assembly Center Limited (UTAC Holdings Ltd.)
• Inventors: Liu, Hao, TOH, Chin Hock, Kolan, Ravi Kanth
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US12/133,377
• Publication Number:
  US 20080303031A1
• Time in Patent Office: 1,391 Days
• Field of Search: 257/686, 257/725, 257/774, 257/785, 257/E23.011, 257/E23.067, 257/E23.08, 257/E23.145, 257/E23.174, 257/700, 257/685, 257/723
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/812 Applying energy for connecting
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Claims

1. An integrated circuit (IC) die comprising:

a die of the IC having first and second major surfaces, wherein the die is a singulated die of a wafer having a plurality of dies; and

at least one unfilled through via within the die, the unfilled through via passing through the major surfaces of the die, the unfilled through via allows passage of air between the major surfaces of the die to serve as a vent to release pressure generated during assembly of the die.

2. The die of claim 1 comprises a plurality of through vias, the vias include conductive materials to form via contacts.

3. The die of claim 1 comprises die contacts on the first or second major surface.

4. The die of claim 1 comprises a through silicon via type die.

5. A chip package comprising:

a carrier substrate having first and second major surfaces, wherein the second major surface comprises a bonding region; and

an IC die attached to the bonding region, wherein the die is a singulated die of a wafer having a plurality of dies, the IC die includes

first and second major surfaces, and

at least one unfilled through via within the die, the unfilled through via passing through the major surfaces of the die to allow passage of air between the major surfaces of the die to serve as a vent to release pressure generated during assembly.

6. The chip package of claim 5 wherein the die comprises a through silicon via type die.

7. The chip package of claim 5 wherein the chip package includes more than one die forming a die stack.

8. The chip package of claim 7 wherein each die of the die stack comprises at least one unfilled via.

9. The chip package of claim 7 wherein the die stack includes a plurality of through vias, the vias include conductive materials to form via contacts.

10. The chip package of claim 7 wherein the top die of the die stack comprises a flip chip.

11. The chip package of claim 5 comprises an underfill material in a cavity in between the die and the carrier.

12. The chip package of claim 11 wherein the underfill material comprises material that includes max fillers, moldable underfills, epoxy mold compound or epoxy.

13. The chip package of claim 5 wherein the carrier further includes carrier vias.

14. The chip package of claim 5 comprises a package cap to encapsulate the die.

15. A device comprising:

an integrated circuit (IC) die which is a singulated die of a wafer having a plurality of dies, wherein the IC die includes first and second major surfaces, wherein one of the major surfaces is an active surface having die contacts; and

an unfilled through via within the die, the unfilled through via passing through the major surfaces of the die to allow passage of air between the major surfaces to serve as a vent to release pressure generated during assembly.

16. The device of claim 15 wherein the die comprises a plurality of unfilled vias.

17. The device of claim 15 comprises a through silicon via type die.

18. The device of claim 16 wherein the die contacts on the active surface are coupled to a die attach region of a carrier substrate.

19. The device of claim 18 wherein the die and carrier substrate are encapsulated to form a package.

20. The device of claim 18 comprises underfill between the die attach region of the carrier substrate and active surface of the die.

21. The device of claim 15 further comprises at least one additional die coupled to the die to form a die stack.

22. The device of claim 21 wherein dies of the die stack comprise unfilled through vias.

23. The device of claim 21 wherein the die stack comprises dies of a same type.

24. The device of claim 21 wherein the die stack comprises at least one die which is of a different type than other dies of the die stack.

25. A device comprising:

a die containing an integrated circuit (IC), wherein the die is a singulated die of a wafer having a plurality of dies, the die having first and second major surfaces; and

at least one unfilled through via within the die, the unfilled through via passing through the major surfaces of the die, the unfilled through via allows passage of air between the major surfaces of the die to serve as a vent to release pressure generated during assembly of the device.

26. The device of claim 25 comprises a plurality of dies coupled to form a die stack, wherein at least one of the dies comprises at least one unfilled through via.

27. The device of claim 25 comprises a plurality of dies coupled to form a die stack, wherein the plurality of dies comprise at least one unfilled through via.

28. The device of claim 26 wherein a bottom die of the die stack is coupled to a carrier substrate of a package.

29. The device of claim 26 wherein unfilled through vias of the dies are not aligned.