Adhesive on wire stacked semiconductor package

• US 8,143,727 B2
• Filed: 11/16/2010
• Issued: 03/27/2012
• Est. Priority Date: 03/09/2001
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Oh, Kwang Seok, Park, Jong Wook, Park, Young Kuk, Min, Byoung Youl
• Primary Examiner(s): Luu, Chuong A.
• Application Number:
  US12/927,533
• Publication Number:
  US 20110089564A1
• Time in Patent Office: 497 Days
• Field of Search: 257/777, 257/686, 257/685, 257/723, 257/737, 257/784, 257/787, 257/779, 257/780, 257/783, 257/789, 257/790, 257/687, 257/786, 438/106
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/4554 Coating
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85186 : connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/85986 : Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 : Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/16 : Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Claims

1. A semiconductor package comprising:

a substrate;

a first semiconductor chip coupled to a surface of the substrate, the first semiconductor chip having first and second surfaces;

input-output pads formed on the second surface of the first semiconductor chip;

first conductive wires connecting the input-output pads of the first semiconductor chip and the substrate;

an adhesive layer coupled to the second surface of the first semiconductor chip, the adhesive layer covering the input-output pads of the first semiconductor chip and parts of the first conductive wires positioned on the input-output pads of the first semiconductor chip;

a second semiconductor chip having first and second surfaces, wherein the second semiconductor chip is coupled to the adhesive layer; and

an insulator between the first surface of the second semiconductor chip and the adhesive layer.

2. A semiconductor package in accordance with claim 1 further comprising:

input-output pads formed on the second surface of the second semiconductor chip; and

second conductive wires connecting the input-output pads of the second semiconductor chip and the substrate.

3. A semiconductor package in accordance with claim 2 further comprising:

a sealing part sealing the first semiconductor chip, the adhesive layer, the second semiconductor chip, the first conductive wires, and the second conductive wires.

4. A semiconductor package in accordance with claim 1 wherein the first semiconductor chip is an edge pad type semiconductor chip in which the input-output pads of the first semiconductor chip are formed at an inner circumference of the second surface.

5. A semiconductor package in accordance with claim 1 wherein the first semiconductor chip is a center pad type semiconductor chip in which the input-output pads of the first semiconductor chip are formed at the center of the second surface.

6. A semiconductor package in accordance with claim 1 wherein the adhesive layer is one selected from a group consisting of:

nonconductive liquid phase adhesive, a nonconductive adhesive tape, and combinations thereof.

7. A semiconductor package in accordance with claim 1 wherein the first conductive wires contact the insulator.

8. A semiconductor package in accordance with claim 1 wherein first ends of the first conductive wires are bonded on the substrate and second ends of the first conductive wires are bonded on the input-output pads of the first semiconductor chip by stitch bonding.

10. A semiconductor package in accordance with claim 8 further comprising supporters formed on the first conductive wires connected on the input-output pads, the supporters supporting the second semiconductor chip.

11. A semiconductor package in accordance with claim 8 wherein the first ends of the first conductive wires are bonded on the substrate by ball bonding.

9. A semiconductor package comprising:

a substrate;

a first semiconductor chip coupled to a surface of the substrate, the first semiconductor chip having first and second surfaces;

input-output pads formed on the second surface of the first semiconductor chip, wherein conductive balls are formed on the input-output pads of the first semiconductor chip;

first conductive wires connecting the input-output pads of the first semiconductor chip and the substrate;

an adhesive layer coupled to the second surface of the first semiconductor chip, the adhesive layer covering the input-output pads of the first semiconductor chip and parts of the first conductive wires positioned on the input-output pads of the first semiconductor chip; and

a second semiconductor chip having first and second surfaces, wherein the second semiconductor chip is coupled to the adhesive layer.

12. A semiconductor package comprising:

a substrate comprising a circuit pattern;

a first semiconductor chip having first and second surfaces, wherein the first surface of the first semiconductor chip is coupled to the substrate,

input-output pads formed on the second surface of the first semiconductor chip;

an adhesive layer coupled to the second surface of the first semiconductor chip and covering the input-output pads of the first semiconductor chip;

a second semiconductor chip having first and second surfaces, wherein the second semiconductor chip is coupled to the adhesive layer;

an insulator between the first surface of the second semiconductor chip and the adhesive layer;

input-output pads formed on the second surface of the second chip;

first conductive wires connecting the input-output pads of the first semiconductor chip and the circuit pattern of the substrate;

second conductive wires connecting the input-output pads of the second semiconductor chip and the circuit pattern of the substrate; and

a sealing part sealing the first semiconductor chip, the adhesive layer, the second semiconductor chip, the first conductive wires, and the second conductive wires.

13. A semiconductor package in accordance with claim 12 wherein the substrate is one selected from a group consisting of a printed circuit board, a circuit tape, a circuit film, a lead frame, and combinations thereof.

15. A semiconductor package in accordance with claim 12 wherein the adhesive layer is one selected from a group consisting of:

nonconductive liquid phase adhesive, a nonconductive adhesive tape, and combinations thereof.

16. A semiconductor package in accordance with claim 12 wherein the first conductive wires contact the insulator.

14. A semiconductor package comprising:

a substrate comprising a circuit pattern;

a first semiconductor chip having first and second surfaces, wherein the first surface of the first semiconductor chip is coupled to the substrate,

input-output pads formed on the second surface of the first semiconductor chip;

an adhesive layer coupled to the second surface of the first semiconductor chip and covering the input-output pads of the first semiconductor chip;

a second semiconductor chip having first and second surfaces, wherein the second semiconductor chip is coupled to the adhesive layer;

input-output pads formed on the second surface of the second chip;

first conductive wires connecting the input-output pads of the first semiconductor chip and the circuit pattern of the substrate;

second conductive wires connecting the input-output pads of the second semiconductor chip and the circuit pattern of the substrate;

a sealing part sealing the first semiconductor chip, the adhesive layer, the second semiconductor chip, the first conductive wires, and the second conductive wires; and

conductive balls coupled to the substrate.

17. A semiconductor package comprising:

a substrate comprising a circuit pattern;

a first semiconductor chip coupled to the substrate, the first semiconductor chip having first and second surfaces;

an input-output pad formed on the second surface of the first semiconductor chip;

a first conductive wire connecting the input-output pad of the first semiconductor chip and the circuit pattern of the substrate;

an adhesive layer coupled to the second surface of the first semiconductor chip, the adhesive layer covering a part of the first conductive wire positioned on the input-output pad of the first semiconductor chip;

a second semiconductor chip having first and second surfaces, wherein the second semiconductor chip is coupled to the adhesive layer; and

an insulator between the first surface of the second semiconductor chip and the adhesive layer.

18. A semiconductor package in accordance with claim 17 further comprising:

an input-output pad formed on the second surface of the second semiconductor chip; and

a second conductive wire connecting the input-output pad of the second semiconductor chip and the circuit pattern of the substrate.