IC with deskewing circuits

• US 8,143,915 B2
• Filed: 11/22/2010
• Issued: 03/27/2012
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US12/952,177
• Publication Number:
  US 20110089969A1
• Time in Patent Office: 491 Days
• Field of Search: 326 37- 41, 326/46, 326/47, 714/700
• US Class Current: 326/46
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments provide a configurable integrated circuit (IC) comprising multiple deskew circuits for delaying data passage. Each of the deskew circuits comprises a stepwise delay circuit with multiple outputs and an input selection circuit with multiple inputs. Multiple outputs connect to multiple inputs.

Claims

1. An integrated circuit (IC) comprising:

a) a plurality of configurable logic circuits for configurably performing a plurality of logical operations to produce data;

b) a configurable routing fabric for configurably connecting the plurality of configurable logic circuits to route said data between the configurable logic circuits; and

c) a plurality of deskew circuits for receiving at least one unaligned subset of said data and temporally aligning and storing the subset of said data, each of said deskew circuits comprising;

i) a stepwise delay circuit for receiving a bit of the unaligned subset of said data and outputting the received bit at a plurality of outputs that correspond to different delays; and

ii) a latency selection circuit comprising a plurality of inputs, wherein at least two of said outputs of the stepwise delay circuit connect to at least two of said inputs of the latency selection circuit.

2. The IC of claim 1, wherein the stepwise delay circuit loads one bit of the unaligned subset of said data once every user design cycle, wherein each of said deskew circuits further comprises a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle of the user design cycle.

3. The IC of claim 1, wherein at least one of said deskew circuits further comprises an incoming data selection circuit for selecting the bit of the unaligned subset of said data from a set of incoming data lines, said incoming data selection circuit comprising (i) an output communicably connected to the stepwise delay circuit of the deskew circuit and (ii) a set of inputs connected to the set of incoming data lines.

4. The IC of claim 1, wherein at least a portion of the unaligned subset of the data produced by the configurable logic circuits is from user design state (UDS) elements that store values that define a user-design state of the IC.

5. The IC of claim 1, wherein the IC comprises a storage circuit for storing a portion of the data produced by the configurable logic circuits, wherein said storing is controlled by the subset of said data that is temporally aligned by the deskew circuits.

6. The IC of claim 1, wherein the plurality of configurable logic circuits are sub-cycle reconfigurable circuits.

7. An integrated circuit (IC) comprising:

a plurality of configurable tiles for configurably performing a plurality of logical operations to produce data;

a plurality of deskew circuits for receiving at least one unaligned subset of said data and temporally aligning and storing the subset of said data, each of said deskew circuits comprising;

i) a stepwise delay circuit for receiving a bit of the unaligned subset of said data from at least one configurable tile and outputting the received bit at a plurality of outputs that correspond to different delays; and

a latency selection circuit comprising a plurality of inputs, wherein at least two of said outputs of the stepwise delay circuit connect to at least two of said inputs of the latency selection circuit.

8. The IC of claim 7, wherein temporally aligning the unaligned subset of said data comprises compensating for a set of delays between a production of the unaligned subset of said data within said IC and an arrival of individual bits of the unaligned subset of said data at said deskew circuits.

9. The IC of claim 7, wherein the stepwise delay circuit loads one bit of the unaligned subset of said data once every user design cycle, wherein each of said deskew circuits further comprises a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle of the user design cycle.

10. The IC of claim 7, wherein the IC comprises a storage circuit for storing a portion of the data produced by the configurable tiles, wherein said storing is controlled by the subset of said data that is temporally aligned by the deskew circuits.

11. The IC of claim 7, wherein the plurality of configurable tiles comprise configurable logic circuits and configurable routing circuits that are sub-cycle reconfigurable circuits.

12. An integrated circuit (IC) comprising:

a) a plurality of configurable logic circuits for configurably performing a plurality of logical operations to produce data;

b) a configurable routing fabric for configurably connecting the plurality of configurable logic circuits to route said data between the configurable logic circuits; and

c) a network comprising;

i) a plurality of multi-input deskew circuits for receiving at least one unaligned subset of said data and temporally aligning and storing the subset of said data; and

ii) a multi-layer transport network for transporting at least a portion of said data to a storage circuit, wherein a plurality of outputs of a set of at least two layers of said multi-layer transport network connect to a plurality of inputs of said plurality of multi-input deskew circuits.

13. The IC of claim 12, wherein substantially all outputs of a first layer of said set of at least two layers of said multi-layer transport network connect to inputs of each of said plurality of multi-input deskew circuits.

14. The IC of claim 13, wherein a first subset of outputs of a second layer of said set of at least two layers connect to inputs of each of a first subset of said plurality of multi-input deskew circuits.

15. The IC of claim 14, wherein a second subset of outputs of the second layer of said set of at least two layers connect to inputs of each of a second subset of said plurality of multi-input deskew circuits.

16. The IC of claim 15, wherein said second subset of said plurality of multi-input deskew circuits comprises about half of said plurality of multi-input deskew circuits.

17. The IC of claim 15, wherein a third subset of outputs of the second layer of said set of at least two layers connect to inputs of each of a third subset of said plurality of multi-input deskew circuits.

18. The IC of claim 15, wherein said first subset of said plurality of multi-input deskew circuits comprises about one third of said plurality of multi-input deskew circuits.

19. The IC of claim 18, wherein said second subset of said plurality of multi-input deskew circuits comprises about one third of said plurality of multi-input deskew circuits.

20. The IC of claim 19, wherein a third subset of said plurality of multi-input deskew circuits comprises about one third of said plurality of multi-input deskew circuits.