Three dimensional inductor and transformer
First Claim
1. A three dimensional on-chip inductor comprising:
- a substrate having a top side and a bottom side, the top side being opposite the bottom side;
a plurality of segments of a first metal layer, the first metal layer being above the top side of the substrate;
a plurality of segments of a second metal layer, the second metal layer being below the bottom side of the substrate;
a first inductor input and a second inductor input; and
a plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input.
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Accused Products
Abstract
A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.
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Citations
23 Claims
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1. A three dimensional on-chip inductor comprising:
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a substrate having a top side and a bottom side, the top side being opposite the bottom side; a plurality of segments of a first metal layer, the first metal layer being above the top side of the substrate; a plurality of segments of a second metal layer, the second metal layer being below the bottom side of the substrate; a first inductor input and a second inductor input; and a plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 22, 23)
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7. A three dimensional on-chip inductor comprising:
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a plurality of segments of a first metal layer; a plurality of segments of a second metal layer; a first inductor input and a second inductor input; and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input; wherein the first inductor input is located in one of the first metal layer and the second metal layer, and the second inductor input is located in a third metal layer.
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10. A three dimensional on-chip transformer comprising:
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a substrate having a top side and a bottom side, the top side being opposite the bottom side; a first on-chip inductor and a second on-chip inductor, each of the first and second on-chip inductors comprising a plurality of first segments in a first metal layer, the first metal layer being above the top side of the substrate; a plurality of second segments in a second metal layer, the second metal layer being below the bottom side of the substrate; a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metal layer and the second metal layer; and a plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input; the first on-chip inductor being inductively coupled to the second on-chip inductor, and the first on-chip inductor not being physically coupled to the second on-chip inductor except through ground. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A three dimensional on-chip electronic device comprising:
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a substrate having a top side and a bottom side, the top side being opposite the bottom side; a first on-chip inductor comprising a first plurality of first layer segments in a first metal layer, the first metal layer being above the top side of the substrate, a first plurality of second layer segments in a second metal layer, the second metal layer being below the bottom side of the substrate, a first inductor input and a first inductor output, and a first plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the first plurality of first layer segments and the first plurality of second layer segments to form a continuous, non-intersecting path between the first inductor input and the first inductor output, the first inductor input and the first inductor output being located in one of the first metal layer and the second metal layer, the first inductor output being coupled to ground; and a second on-chip inductor comprising a second plurality of first layer segments in the first metal layer, a second plurality of second layer segments in the second metal layer, a second inductor input and a second inductor output, and a second plurality of through silicon vias extending from the top side of the substrate to the bottom side of the substrate and coupling the second plurality of first layer segments and the second plurality of second layer segments to form a continuous, non-intersecting path between the second inductor input and the second inductor output, the second inductor input and the second inductor output being located in one of the first metal layer and the second metal layer, the second inductor output being coupled to ground; the first on-chip inductor being inductively coupled to the second on-chip inductor, and the first on-chip inductor not being physically coupled to the second on-chip inductor except through ground. - View Dependent Claims (17, 18, 19, 20, 21)
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Specification