Self-trim and self-test of on-chip values

• US 8,143,953 B2
• Filed: 06/03/2009
• Issued: 03/27/2012
• Est. Priority Date: 05/18/2009
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: von Staudt, Hans Martin, Hulβ, Rolf, Keller, Michael, Burkhardt, Helmut
• Primary Examiner(s): Chang, Joseph
• Assistant Examiner(s): SHIN, JEFFREY M
• Application Number:
  US12/455,530
• Publication Number:
  US 20100289590A1
• Time in Patent Office: 1,028 Days
• Field of Search: 331/1.A, 331/25, 331/111, 331/143, 331/177.R, 331/179, 714/724, 324/750.01, 365/189.09
• US Class Current: 331/1.A
• CPC Class Codes: G01R 31/31903 tester configuration
• CPC Class Codes: G01R 31/31915 In-circuit Testers
• CPC Class Codes: G01R 31/31932 Comparators

Abstract

A self-trim circuit provides a technique to trim a CUT (circuit under trim) using a LSB offset to determine the best digital value to trim the CUT. The self-trim circuit is also used to self-test the digital and analog portions of the self-trim circuitry, whereby the existence of a digital stuck at fault condition is detected. A state machine controls a digital stack to couple digital trim data to the CUT and read the output of a comparator circuit that signifies when a proper digital trim value has been used. Thereafter the proper digital trim value is stored into a nonvolatile memory.

Claims

1. A self-trim circuit, comprising:

a) a circuit under trim (CUT) producing an analog signal and trimmed by a digital self-trim circuit;

b) a compare circuit to compare an output of the CUT to a reference signal;

c) said digital self-trim circuit receives and stores digital trim data to trim the CUT used to produce said output comparable to the reference signal, and said digital self-trim circuit controls said CUT to produce said output to match the reference signal to within a least significant bit (LSB) of the digital trim data, after which said digital circuit creates an offset to the compare circuit to verify the CUT trimmed to a value of the reference signal within the LSB.

2. The circuit of claim 1, wherein the LSB has a block distribution of one LSB to account for semiconductor process variations and effects of minor defects.

3. The circuit of claim 1, wherein the offset is 1.5 least significant bits.

4. The circuit of claim 1, wherein the output of the CUT is a voltage.

5. The circuit of claim 1, wherein the output of the CUT is a current.

6. The circuit of claim 1, wherein the output of the CUT is time, further comprising;

a) frequency, the reciprocal of time; and

b) pulse width.

7. The circuit of claim 6, wherein the CUT is an oscillator in which frequency trimming of the CUT further comprises:

a) a comparison of outputs of two n-bit counters determines a frequency trim of said CUT relative to a reference frequency, wherein a first of the two n-bit counters counts the frequency trim of the CUT and a second of the two n-bit counters counts the reference frequency, wherein the two n-bit counters are reset at the same time to start the two n-bit counters, whereby an output of the first of the two n-bit counters compared to an output of the second of the two n-bit counters; and

b) an offset implemented in the reset of the second of the two n-bit counters after the frequency trim of the CUT reaches the end of the first counter before the reference frequency reaches the end of the second counter to verify the frequency trim within the offset.

8. The circuit of claim 1, wherein said CUT and said digital circuit is located on an integrated circuit chip, wherein said reference signal and said digital data is sourced from automatic test equipment and said trim of the CUT is performed in parallel with other tests performed on the integrated circuit chip by the test equipment.

9. The circuit of claim 1, wherein said digital self-trim circuit further comprises a self-test capability using said trim circuitry, further comprising:

a) a test of said compare circuit, wherein both inputs of said compare circuit are connected to the reference signal or the CUT signal; and

b) a switchable offset of a known value connected to the compare circuit by the digital self-trim circuit and wherein the digital self-trim circuit reads the expected response of the compare circuit for both a positive and a negative value offset.

10. A method of self-test and self-trim, comprising:

a) self-testing a comparator circuit of self trim circuit contained within an integrated circuit device, wherein said self-testing further comprises;

i) connecting a reference signal to both input of the comparator circuit;

ii) applying first a positive, then a negative offset to the comparator circuit; and

iii) reading an output of the comparator circuit with a state machine to detect change of state of the comparator circuit;

b) self-trimming a circuit under trim (CUT) contained within said integrated circuit device, if the comparator circuit passes testing of step a), otherwise rejecting said integrated circuit device;

c) loading a register stack with a plurality of digital trim values to trim the CUT to produce a specified output;

d) coupling an output of the CUT to a first input of the comparator circuit and the reference signal to a second input of the comparator circuit;

e) applying said digital trim values to the CUT, one after another, until output of said comparator circuit changes state;

then

f) applying a verification offset to the comparator circuit to again force output of said comparator circuit to change state and thereby verifying the self-trimming of the CUT is within the verification offset; and

i) storing into a nonvolatile memory the digital trim value causing the state change in comparator circuit output.

11. The method of claim 10, wherein the verification offset is 1.5 least significant bits.

12. The circuit of claim 10, wherein the output of the CUT is voltage.

13. The circuit of claim 10, wherein the output of the CUT is a current.

14. The circuit of claim 10, wherein the output of the CUT is time, further comprising;

a) frequency; and

b) pulse width.

15. The method of claim 10, wherein said register stack is loaded from automatic test equipment.

16. The method of claim 10, wherein said self-trimming of the CUT is controlled by a state machine.

17. An oscillator self trim circuit, comprising:

a) a means for creating a digital signal when an output of a frequency generating circuit reaches a predetermined number of cycles;

b) a means for comparing a first said digital signal created for an oscillator circuit under trim (CUT) and a second said digital signal created for a reference clock;

c) a means for digitally adjusting and thereby trimming the frequency of the CUT, thereby forming a digital trim value for the CUT;

d) a means for offsetting the start condition of said circuitry creating said second digital signal to verify said CUT output frequency trimmed to within said offset; and

e) a means for storing the digital trim value.

18. The self trim circuit of claim 17, wherein said means for creating a digital signal is an n-bit counter, wherein a first n-bit counter counts an output signal of the CUT and a second n-bit counter counts the output signal of reference clock.

19. The self trim circuit of claim 18, wherein said means for comparing the first digital signal and the second digital signal is a flip-flop circuit, wherein the second digital signal clocks the flip-flop to determine when the first digital signal arrives at the flip-flop before the second digital signal clocks the flip-flop.

20. The self trim circuit of claim 17, wherein the means for digitally adjusting the frequency of the CUT is controlled by core logic on the same semiconductor chip as the cut, wherein the core logic comprises a state machine, and a register stack, and communicates with the CUT with digital circuitry.

21. The self trim circuit of claim 17, wherein the means for offsetting the start condition of circuitry the second digital signal produces an offset delay in the reset of the second n-bit counter greater than an equivalent of the least significant bit (LSB) of the digital trim value.

22. The self trim circuit of claim 17, wherein the means for storing the digital trim value comprises a nonvolatile memory connected to core logic controlling the digital trim of the CUT.