Electronic circuit control element with tap element

• US 8,144,484 B2
• Filed: 11/25/2009
• Issued: 03/27/2012
• Est. Priority Date: 05/27/2003
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald R.
• Primary Examiner(s): Vu, Bao Q
• Application Number:
  US12/626,466
• Publication Number:
  US 20100072540A1
• Time in Patent Office: 853 Days
• Field of Search: 363/21.1, 363/21.04, 363/21.12, 363/18, 363/19, 363/20
• US Class Current: 363/21.1
• CPC Class Codes: G05F 1/14 using tap transformers or tap changing inductors as final control devices
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 3/335 using semiconductor devices only
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33553 with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H02M 3/33561 having more than one ouput with independent control

Abstract

A technique for controlling a power supply with power supply control element with a tap element. An example power supply control element includes a power transistor that has first and second main terminals, a control terminal and a tap terminal. A control circuit is coupled to the control terminal. The tap terminal and the second main terminal of the power transistor are to control switching of the power transistor. The tap terminal is coupled to provide a signal to the control circuit substantially proportional to a voltage between the first and second main terminals when the voltage is less than a pinch off voltage. The tap terminal is coupled to provide a substantially constant voltage that is less than the voltage between the first and second main terminals to the control circuit when the voltage between the first and second main terminals is greater than the pinch-off voltage.

Claims

1. A high voltage transistor, comprising:

an N+ drain region;

an N+ source region;

an N+ tap region;

a P type body region adjoining the N+ source region;

an N−

drift region extending from the drain region to the P type body region;

an N−

tap drift region extending from the N+ drain region to the N+ tap region, wherein the N+ tap region adjoins the N−

tap drift region at an end of the N−

tap drift region opposite the N+ drain region; and

an insulated gate adjacent the P type body region.

2. The high voltage transistor of claim 1, further comprising a tap element coupled to the N+ tap region.

3. The high voltage transistor of claim 1, further comprising a P type region extending from the N+ drain region to the P type body region and wherein the P type region is disposed between the N−

drift region and the N−

tap drift region.

4. The high voltage transistor of claim 1, further comprising a field plate disposed between the N−

drift region and the N−

tap drift region.

5. The high voltage transistor of claim 4, further comprising:

a source electrode coupled to the N+ source region and the field plate;

a drain electrode coupled to the N+ drain region; and

a gate electrode coupled to the insulated gate.

6. The high voltage transistor of claim 4, wherein the field plate is disposed in dielectric material comprising silicon dioxide.

7. The high voltage transistor of claim 1, wherein a voltage between the N+ tap region and the N+ source region is proportional to a voltage between the N+ drain region and the N+ source region when the voltage between the N+ drain region and the N+ source region is less than a pinch off voltage.

8. The high voltage transistor of claim 1, wherein the N−

tap drift region is configured to pinch off the voltage difference between the N+ tap region and the N+ source region when the voltage difference between the N+ drain region and the N+ source region is greater than a pinch off voltage.

9. The high voltage transistor of claim 1, wherein a voltage between the N+ tap region and the N+ source region is substantially constant when the voltage difference between the N+ drain region and the N+ source region is greater than a pinch off voltage.

10. The high voltage transistor of claim 1, further comprising:

a source electrode coupled to the N+ source region;

a drain electrode coupled to the N+ drain region; and

a gate electrode coupled to the insulated gate.

11. The high voltage transistor of claim 1, wherein the N−

tap drift region has a construction and doping profile that is substantially similar to the N−

drift region.

12. The high voltage transistor of claim 1, wherein the N−

tap drift region has a construction that is different than the N−

drift region.

13. The high voltage transistor of claim 1, wherein the N−

tap drift region has a dimension that is different than the N−

drift region.

14. The high voltage transistor of claim 1, wherein the N−

tap drift region has a doping profile that is different than the N−

drift region.