Write operation for spin transfer torque magnetoresistive random access memory with reduced bit cell size

• US 8,144,509 B2
• Filed: 06/27/2008
• Issued: 03/27/2012
• Est. Priority Date: 06/27/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc., Yonsei University
• Original Assignee: Qualcomm, Inc.
• Inventors: Jung, Seong-Ook, Sani, Mehdi Hamidi, Kang, Seung H., Yoon, Sei Seung
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Byrne, Harry W
• Application Number:
  US12/163,359
• Publication Number:
  US 20090323404A1
• Time in Patent Office: 1,369 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/225.5, 365/243.5, 216/22, 257/421, 257/E21.665, 483/3, 977933-935
• US Class Current: 365/171
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y10S 977/933 Spintronics or quantum computing

Abstract

Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.

Claims

1. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) comprising:

a bit cell array having a source line substantially parallel to a word line coupled to a first row of bit cells, wherein the source line is substantially perpendicular to bit lines coupled to the first row of bit cells.

2. The STT-MRAM of claim 1, further comprising:

a word line coupled to a second row of bit cells, wherein the source line is coupled to the second row of bit cells.

3. The STT-MRAM of claim 1, wherein the source line is disposed between the word line of the first row of bit cells and the word line of second row of bit cells.

4. The STT-MRAM of claim 1, further comprising:

logic configured to establish a low voltage on a bit line of a selected bit cell in the first row of bit cells coupled to the word line and the source line and configured to establish a high voltage on bit lines of unselected bit cells in the first row of bit cells coupled to the word line and the source line.

5. The STT-MRAM of claim 4, wherein the high voltage is a supply voltage level and the low voltage is a ground level.

6. The STT-MRAM of claim 4, wherein the logic configured to establish a low voltage on the bit line of the selected cell comprises:

bit line select logic coupled to a plurality of bit line drivers.

7. The STT-MRAM of claim 6, wherein the bit line select logic is configured to receive a plurality of column address signals and a data high signal.

8. The STT-MRAM of claim 7, wherein each of the plurality of bit line drivers is coupled to an associated bit line based on a select signal from the bit line select logic.

9. The STT-MRAM of claim 8, wherein the select signals are derived from the column select address signals and complements of the column select signals.

10. The STT-MRAM of claim 9, wherein the column select address signals and their complements are provided to NAND gates and the outputs of the NAND gates are input to respective bit line drivers.

11. The STT-MRAM of claim 2, further comprising:

logic configured to drive the word lines of the first and second row of bit cells and logic configured to select the source line.

12. The STT-MRAM of claim 11, wherein the logic to drive the word lines and the logic configured to select the source line are combined.

13. The STT-MRAM of claim 12, wherein the logic configured to drive the word lines of the first and second row of bit cells are coupled to row address inputs and logic configured to select the source line is coupled to the logic configured to drive the word lines.

14. The STT-MRAM of claim 13, wherein the logic configured to drive the word lines of the first and second row of bit cells comprises:

a first NAND gate coupled to two row address inputs and having an output coupled to a first inverter to drive the word line of the first row of bit cells; and

a second NAND gate coupled to two row address inputs and having an output coupled to a second inverter to drive the word line of the second row of bit cells.

15. The STT-MRAM of claim 13, wherein the logic configured to select the source line comprises a third NAND gate having inputs coupled to the outputs of the first and second NAND gate and an output to generate a source line select signal.

16. A method comprising:

forming a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array having a source line substantially parallel to a word line of a first row of bit cells and substantially perpendicular to bit lines coupled to the first row of bit cells.

17. The method of claim 16, further comprising:

forming a word line coupled to a second row of bit cells substantially in parallel with the first row of bit cells; and

coupling the source line to the second row of bit cells.

18. The method of claim 16, further comprising:

disposing the source line between the word lines of the first and second row of bit cells.

19. A method for writing data in a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) having a source line substantially parallel to a word line coupled to a first row of bit cells, wherein the source line is substantially perpendicular to bit lines coupled to the first row of bit cells, the method comprising:

establishing a low voltage on a bit line of a selected bit cell coupled to the word line of the first row of bit cells and the source line; and

establishing a high voltage on bit lines of unselected bit cells coupled to the word line of the first row of bit cells and the source line.

20. The method of claim 19, wherein the high voltage is a supply voltage level and the low voltage is a ground level.

21. The method of claim 19, wherein establishing a low voltage on the bit line of the selected cell comprises:

generating bit line select signals; and

activating or deactivating bit line drivers based on the bit line select signals.

22. The method of claim 21, wherein the bit line select signals are generated from a plurality of column address signals and a data high signal.

23. The method of claim 22, wherein each of the plurality of bit line drivers is coupled to an associated bit line based on one of the bit line select signals.

24. The method of claim 22, wherein the bit line select signals are derived from the column address signals and complements of the column address signals.

25. The method of claim 24, wherein the column select addresses signals and their complements are provided to NAND gates and the outputs of the NAND gates are input to respective bit line drivers.

26. A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) having a source line substantially parallel to a word line coupled to a first row of bit cells, wherein the source line is substantially perpendicular to bit lines coupled to the first row of bit cells, the STT-MRAM comprising:

means for establishing a low voltage on a bit line of a selected bit cell coupled to the word line of the first row of bit cells and the source line; and

means for establishing a high voltage on bit lines of unselected bit cells coupled to the word line of the first row of bit cells and the source line.

27. The STT-MRAM of claim 26, wherein the means for establishing a low voltage on the bit line of the selected cell comprises:

means for generating bit line select signals; and

means for activating or deactivating bit line drivers based on the bit line select signals.

28. The STT-MRAM of claim 27, wherein the means for generating the bit line select signals receives a plurality of column address signals and a data high signal.

29. The STT-MRAM of claim 27, wherein the bit line drivers are coupled to column address signals and complements of the column address signals.