Balanced sense amplifier for single ended bitline memory architecture
First Claim
1. A memory device comprising:
- a balanced differential sense amplifier;
a first input of the balanced differential sense amplifier coupled to a first single-ended bit line of a selected memory bank;
a second input of the balanced differential sense amplifier coupled to a second single-ended bit line from an unselected memory bank;
a first voltage adder/subtractor coupled to a first bank select signal and the first input of the balanced differential sense amplifier; and
a said second voltage adder/subtractor coupled to a second bank select signal and the second input of the balanced differential sense amplifier.
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Accused Products
Abstract
A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.
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Citations
20 Claims
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1. A memory device comprising:
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a balanced differential sense amplifier; a first input of the balanced differential sense amplifier coupled to a first single-ended bit line of a selected memory bank; a second input of the balanced differential sense amplifier coupled to a second single-ended bit line from an unselected memory bank; a first voltage adder/subtractor coupled to a first bank select signal and the first input of the balanced differential sense amplifier; and a said second voltage adder/subtractor coupled to a second bank select signal and the second input of the balanced differential sense amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device, comprising:
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a first memory bank; a second memory bank; a balanced differential sense amplifier coupled between the first and second memory banks; a first input of the balanced differential sense amplifier coupled to a first single-ended bit line of a selected one of the first and second memory banks; a second input of the balanced differential sense amplifier coupled to a second single ended bit line from an unselected one of the first and second memory banks; a first voltage adder/subtractor configured to connect a first signal derived from a bank select signal to the first input of the balanced differential sense amplifier; and a second voltage adder/subtractor configured to connect a second signal derived from an inversion of the bank select signal to the second input of the balanced differential sense amplifier, wherein the selection of one of the first and second memory banks produces an active level change at one of the first and second inputs. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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generating an active level change on one of first and second signal lines for a balanced differential sense amplifier coupled between first and second memory banks whenever one of the first and second memory banks is selected; and coupling the active level change to a node within a balanced differential sense amplifier that corresponds to a memory cell within the selected one of the first and second memory banks. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification