Balanced sense amplifier for single ended bitline memory architecture

• US 8,144,537 B2
• Filed: 11/11/2009
• Issued: 03/27/2012
• Est. Priority Date: 11/11/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Pvt Ltd. (STMicroelectronics NV)
• Inventors: Mishra, Anand Kumar, Rawat, Harsh
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US12/616,696
• Publication Number:
  US 20100172199A1
• Time in Patent Office: 867 Days
• Field of Search: 365/203, 365/205, 365/207, 365/208, 365/230.03, 708/706, 714/5.11, 257/312
• US Class Current: 365/203
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input receives a reference voltage provided by a corresponding single bit-line memory cell from a complementary memory bank. A supporting voltage is added-to/subtracted-from the reference voltage by providing a “bump” or “dip” mechanism or by utilizing a charge-sharing structure, in order to compensate for the variation in the sensed bit-line voltage over the duration of the sensing interval as well as for the disparity in voltage level from cell to cell.

Claims

1. A memory device comprising:

a balanced differential sense amplifier;

a first input of the balanced differential sense amplifier coupled to a first single-ended bit line of a selected memory bank;

a second input of the balanced differential sense amplifier coupled to a second single-ended bit line from an unselected memory bank;

a first voltage adder/subtractor coupled to a first bank select signal and the first input of the balanced differential sense amplifier; and

a said second voltage adder/subtractor coupled to a second bank select signal and the second input of the balanced differential sense amplifier.

2. The system as claimed in claim 1, wherein the first and second voltage adders/subtractors are each a capacitor.

3. The system as claimed in claim 1, wherein the first and second voltage adders/subtractors are each a device capacitance of a MOS device.

4. The system as claimed in claim 1, wherein the first and second voltage adders/subtractors are each is a device capacitance of a poly to n-well device.

5. The system as claimed in claim 1, further comprising:

logic gate configured to provide an active level change to one of the first and second inputs when the selected memory bank is selected.

6. The system as claimed in claim 1, further comprising:

a first pass gate configured to selectively connect the first voltage adder/subtractor to the first input; and

a second pass gate configured to selectively connect the second voltage adder/subtractor to the second input.

7. The system as claimed in claim 6, wherein the first and second pass gates are each an MOS switch.

8. A memory device, comprising:

a first memory bank;

a second memory bank;

a balanced differential sense amplifier coupled between the first and second memory banks;

a first input of the balanced differential sense amplifier coupled to a first single-ended bit line of a selected one of the first and second memory banks;

a second input of the balanced differential sense amplifier coupled to a second single ended bit line from an unselected one of the first and second memory banks;

a first voltage adder/subtractor configured to connect a first signal derived from a bank select signal to the first input of the balanced differential sense amplifier; and

a second voltage adder/subtractor configured to connect a second signal derived from an inversion of the bank select signal to the second input of the balanced differential sense amplifier,

wherein the selection of one of the first and second memory banks produces an active level change at one of the first and second inputs.

9. The memory device as claimed in claim 8, wherein the first and second voltage adders/subtractors each comprise a capacitance.

10. The memory device as claimed in claim 9, wherein the capacitance is a device capacitance of an MOS device.

11. The memory device as claimed in claim 10, wherein the device capacitance is a gate capacitance of a poly to n-well device.

12. The memory device as claimed in claim 8, further comprising:

a logic configured to provide, in response to the bank select signal, an active level change to on one of the first and second signals when the selected memory bank is selected.

13. The memory device as claimed in claim 8, is further comprising:

a first pass gate configured to selectively connect the first voltage adder/subtractor to the first input; and

a second pass gate configured to selectively connect the second voltage adder/subtractor to the second input.

14. The memory device as claimed in claim 8, wherein the first and second voltage adders/subtractors each comprise a first capacitance device and a second device capacitance.

15. A method, comprising:

generating an active level change on one of first and second signal lines for a balanced differential sense amplifier coupled between first and second memory banks whenever one of the first and second memory banks is selected; and

coupling the active level change to a node within a balanced differential sense amplifier that corresponds to a memory cell within the selected one of the first and second memory banks.

16. The method as claimed in claim 15, wherein a voltage differential within the balanced differential sense amplifier is generated by a charge sharing mechanism operating on internal sensing nodes of the balanced differential sense amplifier in response to a single-ended bank select signal.

17. The method as claimed in claim 15, further comprising:

providing the active level change to a coupler when the selected one of the first and second memory banks is selected, the coupler adding or subtracting a voltage to the node.

18. The method as claimed in claim 17, wherein the coupler comprises a pass gate.

19. The method as claimed in claim 17, wherein the coupler comprises a capacitor capacitance.

20. The method as claimed in claim 17, wherein the capacitance is a device capacitance of a MOS device.