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Balanced sense amplifier for single ended bitline memory architecture

  • US 8,144,537 B2
  • Filed: 11/11/2009
  • Issued: 03/27/2012
  • Est. Priority Date: 11/11/2008
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • a balanced differential sense amplifier;

    a first input of the balanced differential sense amplifier coupled to a first single-ended bit line of a selected memory bank;

    a second input of the balanced differential sense amplifier coupled to a second single-ended bit line from an unselected memory bank;

    a first voltage adder/subtractor coupled to a first bank select signal and the first input of the balanced differential sense amplifier; and

    a said second voltage adder/subtractor coupled to a second bank select signal and the second input of the balanced differential sense amplifier.

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