Serial radio frequency to baseband interface with programmable clock

• US 8,144,810 B2
• Filed: 02/19/2003
• Issued: 03/27/2012
• Est. Priority Date: 02/19/2003
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Inventors: Gronemeyer, Steve, Tso, Robert
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): Dsouza, Adolf
• Application Number:
  US10/369,853
• Publication Number:
  US 20040162102A1
• Time in Patent Office: 3,324 Days
• Field of Search: 375/220, 375/257, 375/316, 455/550
• US Class Current: 375/316
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

An interface between an RF processing section and a baseband processing section supports general purpose message transmission as well as satellite positioning system signal sample transmission between the RF processing section and the baseband processing section. The interface includes a bi-directional message serial interface and a data serial interface. The complexity of the data serial interface may be minimized by using a single data bit signal line in the data serial interface.

Claims

1. A radio frequency (RF) to baseband interface coupling an RF section for processing RF signals to a baseband section for processing baseband signals, the interface comprising:

a bi-directional message serial interface for communicating multi-purpose messages between the RF section and the baseband section; and

a data serial interface for communicating signal sample data from the RF section to the baseband section, the data serial interface comprising a data clock signal line and a single data bit signal line to carry a data clock signal and to serially carry the signal sample data, respectively, the signal sample data including sign bits and magnitude bits,

wherein the data clock signal line carries the data clock signal comprising rising edges and falling edges, and the sign bits are valid on the falling edges of the data clock signal and the magnitude bits are valid on the rising edges of the data clock signal, each rising and falling edge including a pairing of the sign and magnitude bits.

2. The interface of claim 1, wherein the message serial interface comprises a message-in signal line, a message-out signal line and a message clock signal line.

3. The interface of claim 2, wherein the message serial interface further comprises a slave-select signal line.

4. A method for interfacing a radio frequency (RF) section for processing RF signals to a baseband section for processing baseband signals, the method comprising the steps of:

serially communicating multi-purpose messages, on a message serial interface, bi-directionally between the RF section and the baseband section; and

serially communicating signal sample data, on a single data bit signal line, from the RF section to the baseband section, using a data clock signal line to facilitate shifting the signal sample date in between the RF section and the baseband section, the signal sample data including sign bits and magnitude bits,

wherein the data clock signal line carries the data clock signal comprising rising edges and falling edges, and the sign bits are valid on the falling edges of the data clock signal and the magnitude bits are valid on the rising edges of the data clock signal, each rising and falling edge including a pairing of the sign and magnitude bits.

5. The method of claim 4, wherein the step of serially communicating messages comprises the step of serially communicating messages using a message-in signal line, a message-out signal line and a message clock signal line.

6. A radio frequency (RF) to baseband interface coupling an RF section for processing RF signals to a baseband section for processing baseband signals, the interface comprising:

a bi-directional message serial interface for communicating between the RF section and the baseband section, the message serial interface comprising;

a message clock line that facilitates shifting data bits in between the RF section and the baseband section;

a message-in signal line and a message-out signal line, each carrying the data bits between the RF section and the baseband section; and

a slave select signal line that facilitates transferring the timing of shifting the data bits in between the RF section and the baseband section, wherein the message-out signal line carries an output bit stream representing a multipurpose message selected from a predefined RF section message group, the predefined RF section message group comprising an RF section power control message and an RF section test message, wherein the predefined message group further comprises an RF section programmable clock synthesizer message, which is used to generate different reference frequencies.

7. The interface of claim 6, wherein the programmable clock synthesizer message comprises a reference divider value.

8. The interface of claim 7, wherein the reference divider value is an integer divider value.

9. The interface of claim 7, wherein the reference divider value is a fractional divider value.

10. The interface of claim 6, wherein the predefined message group further comprises a clock output selection message for selecting a message clock for the message clock line.

11. The interface of claim 6, wherein the message-in signal line carries an input bit stream representing a message selected from a predefined baseband section message group, the predefined baseband section message group comprising a clock status message and an analog measurement message.

12. The interface of claim 11, wherein the predefined baseband section message group further comprises a channel conversion count message.

13. The interface of claim 11, wherein the analog measurement message comprises an analog measurement message for at least one of a plurality of analog input channels.

14. The interface of claim 6, further comprising a data serial interface further comprising a data clock signal line and a single data bit signal line to carry a data clock signal and to serially carry the signal sample data from the RF section to the baseband section, respectively, the signal sample data including sign bits and magnitude bits.

15. The interface of claim 14, wherein:

the data clock signal line carries the data clock signal comprising rising edges and falling edges; and

the sign bits are valid on the rising edges of the data clock signal and the magnitude bits are valid on the falling edges of the data clock signal, each rising and falling edge including a pairing of the sign and magnitude bits.

16. An RF front end for a satellite positioning system, receiver, the front end comprising:

an RF processing section comprising an RF input for receiving satellite positioning system signals; and

an RF to baseband interface coupled to the RF processing section, the interface comprising;

a bi-directional message serial interface for communicating multi-purpose messages between the RF processing section and a baseband processing section; and

a data serial interface for communicating signal sample data from the RF processing section to the baseband processing section, the data serial interface comprising a data clock signal line and a single data bit signal line to carry a data clock signal and to serially carry the signal sample data, respectively, the signal sample data including sign bits and magnitude bits,

wherein the data clock signal line carries the data clock signal comprising rising edges and falling edges, and the sign bits are valid on the falling edges of the data clock signal and the magnitude bits are valid on the rising edges of the data clock signal, each rising and falling edge including a pairing of the sign and magnitude bits.

17. The RF front end of claim 16, wherein the RF processing section and the RF to baseband interface are implemented as an individual single integrated circuit (IC).

18. The RF front end of claim 16, wherein the message serial interface comprises:

a message clock line;

a message-in signal line and a message-out signal line; and

wherein the message-out signal line carries an output bit stream representing a message selected from a predefined RF section message group.

19. The RF front end of claim 18, wherein the RF section message group comprises an RF section power control message and an RF section test message.

20. The RF front end of claim 19, wherein the predefined message group further comprises a clock output selection message for selecting a message clock for the message clock line.

21. The RF front end of claim 18, wherein the message-in signal line carries an input bit stream representing a message selected from a predefined baseband section message group, the predefined baseband section message group comprising a clock status message and an analog measurement message.

22. The RF front end of claim 21, wherein the analog measurement message comprises an analog measurement message for at least one of a plurality of analog input channels.

23. A baseband back end for a satellite positioning system receiver, the back end comprising:

a baseband processing section comprising at least one address line, at least one data line, and at least one control line for communicating with a digital device; and

an RF to baseband interface coupled to the baseband processing section, the interface comprising;

a bi-directional message serial interface for communicating multi-purpose messages between an RF processing section and the baseband processing section; and

a data serial interface for communicating signal sample data from the RF processing section to the baseband processing section, the data serial interface comprising a data clock signal line and a single data bit signal line to carry a data clock signal and to serially carry the signal sample data, respectively, the signal sample data including sign bits and magnitude bits,

wherein the data clock signal line carries the data clock signal comprising rising edges and falling edges, and the sign bits are valid on the falling edges of the data clock signal and the magnitude bits are valid on the rising edges of the data clock signal, each rising and falling edge including a pairing of the sign and magnitude bits.

24. The baseband back end of claim 23, wherein the baseband processing section and the RF to baseband interface are implemented as an individual single IC.

25. The baseband back end of claim 23, wherein the message serial interface comprises:

a message clock line;

a message-in signal line and a message-out signal line; and

wherein the message-out signal line carries an output bit stream representing a message selected from a predefined RF section message group.

26. The baseband back end of claim 25, wherein the RF section message group comprises an RF section power control message and an RF section test message.

27. The baseband back end of claim 26, wherein the predefined message group further comprises a clock output selection message for selecting a message clock for the message clock line.

28. The baseband back end of claim 25, wherein the message-in signal line carries an input bit stream representing a message selected from a predefined baseband section message group, the predefined baseband section message group comprising a clock status message and an analog measurement message.

29. The baseband back end of claim 28, wherein the analog measurement message comprises an analog measurement message for at least one of a plurality of analog input channels.

30. A satellite positioning system receiver comprising:

an RF front end comprising an RF processing section and an RF input for receiving satellite positioning system signals;

a baseband back end comprising a baseband processing section and at least one address, data, and control line for communicating with a digital device; and

an RF to baseband interface coupled between the RF processing section and the baseband processing section, the interface comprising;

a bi-directional message serial interface for communicating multi-purpose messages between the RF processing section and the baseband processing section; and

a data serial interface for communicating signal sample data from the RF processing section to the baseband processing section, the data serial interface comprising a data clock signal line and a single data bit signal line to carry a data clock signal and to serially carry the signal sample data, respectively, the signal sample data including sign bits and magnitude bits,

wherein the data clock signal line carries the data clock signal comprising rising edges and falling edges, and the sign bits are valid on the falling edges of the data clock signal and the magnitude bits are valid on the rising edges of the data clock signal, each rising and falling edge including a pairing of the sign and magnitude bits.

31. The satellite positioning system receiver of claim 30, wherein the RF processing section, the RF input, and the RF to baseband interface are implemented as an individual single IC.

32. The satellite positioning system receiver of claim 30, wherein the message serial interface comprises:

a message clock line;

a message-in signal line and a message-out signal line; and

wherein the message-out signal line carries an output bit stream representing a message selected from a predefined RF section message group.

33. The satellite positioning system receiver of claim 32, wherein the message-in signal line carries an input bit stream representing a message selected from a predefined baseband section message group, the predefined baseband section message group comprising a clock status message and an analog measurement message.

34. The satellite positioning system receiver of claim 33, wherein the analog measurement message comprises an analog measurement message for at least one of a plurality of analog input channels.

35. The satellite positioning system receiver of claim 32, wherein the RF section message group comprises an RF section power control message and an RF section test message.

36. The satellite positioning system receiver of claim 35, wherein the predefined message group further comprises a clock output selection message for selecting a message clock for the message clock line.

37. The satellite positioning system receiver of claim 30, wherein the baseband processing section and the RF to baseband interface are implemented as an individual single IC.