Adaptive bandwidth utilization over fabric links

• US 8,145,787 B1
• Filed: 10/16/2001
• Issued: 03/27/2012
• Est. Priority Date: 10/16/2001
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Rose, Kenneth, Jacobs, Mick, Batra, Jatin
• Primary Examiner(s): TANG, KAREN C
• Application Number:
  US09/978,475
• Time in Patent Office: 3,815 Days
• Field of Search: 370/229, 370/235, 370/412, 370/468, 370/236, 370/232, 370/371, 370/369, 370/230, 370/231, 709/235, 710/34, 710/52, 710/240
• US Class Current: 709/235
• CPC Class Codes: H04L 49/505 Corrective measures
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9084 Reactions to storage capacity overflow

Abstract

Disclosed is a method and apparatus for adapting bandwidth utilization over fabric links. In one embodiment of the method, a transmitting device transmits data at a first non-zero rate to a memory for storage therein during a first period of time. The transmitting device then transmits data at a second non-zero rate to the memory for storage therein during a second period of time. The second period of time is subsequent to the first period of time, and the second non-zero rate is greater than or less than the first non-zero rate. This method may find application in switching network where the transmitting device is contained in a switching fabric, the memory is a FIFO buffer contained in a line card coupled to the switching fabric via a data link, and where the transmitter transmits data via the data link to the FIFO buffer for storage therein.

Claims

1. A method comprising:

receiving data from a transmitting device transmitting data at a first non-zero rate to a memory for storage therein during a first period of time;

generating a first data quantity value representing a quantity of data stored in the memory at a first point in time,

comparing the first data quantity value to a first predetermined value;

causing the transmitting device to transmit data at a second non-zero rate to the memory for storage therein during a second period of time, in response to the comparing;

modifying the first predetermined value in response at least in part to the comparing the first data quantity value to the first predetermined value;

wherein the second period of time is subsequent to the first period of time; and

wherein the second non-zero rate is greater than the first non-zero rate;

wherein the modifying the first predetermined value comprises subtracting a set value from the first predetermined value thereby generating a new first predetermined value.

2. The method of claim 1 wherein the memory device comprises a FIFO buffer.

3. The method of claim 1 wherein the transmitting device is contained in a switching fabric, wherein the memory is contained in a line card coupled to the switching fabric via a data link, and wherein the transmitter transmits data via the data link to the memory for storage therein.

4. The method of claim 1 further comprising:

generating a rate control signal; and

transmitting the rate control signal to the transmitting device to instruct the transmitting device to stop transmitting data at the first non-zero rate and start transmitting data at the second non-zero rate;

wherein the transmitting device stops transmitting data to the memory device at the first data rate and starts transmitting data to the memory device at the second data rate in response to the transmitting device receiving the rate control signal.

5. The method of claim 4 further comprising:

comparing the first data quantity value to a plurality of predetermined values, wherein the first predetermined value is one of the plurality of first predetermined values;

wherein the rate control signal is generated in response to comparing the first data quantity value to the plurality of predetermined values.

6. The method of claim 4 further comprising:

generating a second data quantity value representing a quantity of data stored in the memory device at a second point in time, wherein the second point in time is prior to the first point in time;

comparing the first data quantity value to the second data quantity value;

wherein the rate control signal is generated only if the first data quantity value is not equal to the second data quantity value.

7. The method of claim 1 wherein generating the first data quantity value comprises:

generating total data input count at the first point in time, wherein the total data input count represents a quantity of data input to the memory device during a period of time ending in the first point in time;

generating total data output count at the first point in time, wherein the total data output count represents a quantity of data output from the memory device during the period of time ending in the first point in time;

subtracting the total data output count from total data input count.

8. The method of claim 1 wherein the causing comprises:

transmitting a rate control signal to the transmitting device to instruct the transmitting device to stop transmitting data at the first non-zero rate and start transmitting data at the second non-zero rate, wherein

the transmitting device stops transmitting data to the memory device at the first data rate and starts transmitting data to the memory device at the second data rate in response to the transmitting device receiving the rate control signal.

9. The method of claim 8 further comprising:

comparing the first data quantity value to a plurality of predetermined values, wherein the first predetermined value is one of the plurality of first predetermined values;

wherein the rate control signal is generated in response to comparing the first data quantity value to the plurality of predetermined values.

10. The method of claim 1 further comprising

the transmitting device transmitting data at a third non-zero rate to the memory for storage therein during a third period of time;

wherein the third period of time is subsequent to the second period of time, and wherein the third non-zero rate is greater than the second non-zero rate.

11. An apparatus comprising:

a memory device configured to receive data from a transmitting device for storage therein;

a first circuit configured to generate and transmit a rate control signal instructing the transmitting device to stop transmitting data to the memory device at a first non-zero rate and to begin transmitting data to the memory device at a second non-zero rate wherein the second non-zero rate is greater than the first non-zero rate;

a second circuit for generating a first data quantity value representing a quantity of data stored in the memory device at a first point in time;

a first comparing circuit for comparing the first data quantity value to a first predetermined value, wherein the first circuit generates the rate control signal in response to the comparing; and

a circuit for modifying the first predetermined value in response at least in part to the comparing the first data quantity value to the first predetermined value;

wherein the modifying the first predetermined value comprises subtracting a set value from the first predetermined value thereby generating a new first predetermined value.

12. The apparatus of claim 11 wherein the memory device comprises a FIFO buffer.

13. The apparatus of claim 11 further comprising the transmitting device, wherein the transmitting device is contained in a switching fabric, wherein the memory is contained in a line card coupled to the switching fabric via a data link, and wherein the transmitter transmits data via the data link to the memory for storage therein.

14. The apparatus of claim 11 further comprising:

a plurality of comparing circuits, each one of which is configured to compare the first data quantity value to a respective one of a plurality of predetermined values, wherein the first comparing circuit is one of the plurality of comparing circuits, and wherein the first predetermined value is one of the plurality of first predetermined values;

wherein the first circuit generates the rate control signal in response to comparing the first data quantity value to the plurality of predetermined values.

15. The apparatus of claim 11 further comprising:

a third circuit for generating a second data quantity value representing a quantity of data stored in the memory device at a second point in time, wherein the second point in time is prior to the first point in time;

a second comparing circuit for comparing the first data quantity value to the second data quantity value;

wherein the first circuit generates the rate control signal only if the first data quantity value is not equal to the second data quantity value.

16. The apparatus of claim 15 wherein the first and second circuits are the same circuits.

17. An apparatus comprising:

a memory device configured to receive data from a transmitting device for storage therein;

a first means for generating and transmitting a rate control signal instructing the transmitting device to stop transmitting data to the memory device at a first non-zero rate and to begin transmitting data to the memory device at a second non-zero rate wherein the second non-zero rate is greater than the first non-zero rate;

a second means for generating a first data quantity value representing a quantity of data stored in the memory device at a first point in time;

a third means for comparing the first data quantity value to a first predetermined value; and

a means for modifying the first predetermined value in response at least in part to the comparing the first data quantity value to the first predetermined value;

wherein the first means generates the rate control signal in response to the comparing;

wherein the modifying the first predetermined value comprises subtracting a set value from the first predetermined value thereby generating a new first predetermined value.

18. The apparatus of claim 17 wherein the memory device comprises a FIFO buffer.

19. The apparatus of claim 17 further comprising the transmitting device, wherein the transmitting device is contained in a switching fabric, wherein the memory is contained in a line card coupled to the switching fabric via a data link, and wherein the transmitter transmits data via the data link to the memory for storage therein.

20. The apparatus of claim 17 further comprising:

a fourth means for generating a second data quantity value representing a quantity of data stored in the memory device at a second point in time, wherein the second point in time is prior to the first point in time;

a fifth means for comparing the first data quantity value to the second data quantity value;

wherein the first means generates the rate control signal only if the first data quantity value is not equal to the second data quantity value.

21. A method comprising:

receiving data from a transmitting device transmitting data at a first non-zero rate to a memory for storage therein during a first period of time;

generating a rate control signal by

generating a first data quantity value representing a quantity of data stored in the memory at a first point in time,

comparing the first data quantity value to a first predetermined value, wherein the rate control signal is generated in response to the comparing;

causing the transmitting device to transmit data at a second non-zero rate to the memory for storage therein during a second period of time, wherein

the causing comprises transmitting the rate control signal to the transmitting device; and

modifying the first predetermined value in response at least in part to the comparing the first data quantity value to the first predetermined value;

wherein the second period of time is subsequent to the first period of time; and

wherein the second non-zero rate is less than the first non-zero rate;

wherein the modifying the first predetermined value comprises subtracting a set value from the first predetermined value thereby generating a new first predetermined value.

22. The method of claim 21 further comprising:

transmitting the rate control signal to the transmitting device to instruct the transmitting device to stop transmitting data at the first non-zero rate and start transmitting data at the second non-zero rate; and

wherein the transmitting device stops transmitting data to the memory device at the first data rate and starts transmitting data to the memory device at the second data rate in response to the transmitting device receiving the rate control signal.

23. The method of claim 22 further comprising:

comparing the first data quantity value to a plurality of predetermined values, wherein the first predetermined value is one of the plurality of first predetermined values;

wherein the rate control signal is generated in response to comparing the first data quantity value to the plurality of predetermined values.

24. An apparatus comprising:

a memory device configured to receive data from a transmitting device for storage therein;

a first circuit configured to generate and transmit a rate control signal instructing the transmitting device to stop transmitting data to the memory device at a first non-zero rate and to begin transmitting data to the memory device at a second non-zero rate, wherein the second non-zero rate is less than the first non-zero rate;

a second circuit for generating a first data quantity value representing a quantity of data stored in the memory device at a first point in time;

a first comparing circuit for comparing the first data quantity value to a first predetermined value, wherein the first circuit generates the rate control signal in response to the comparing; and

a circuit for modifying the first predetermined value in response at least in part to the comparing the first data quantity value to the first predetermined value;

wherein the modifying the first predetermined value comprises subtracting a set value from the first predetermined value thereby generating a new first predetermined value.