Wake-and-go mechanism with system bus response

• US 8,145,849 B2
• Filed: 02/01/2008
• Issued: 03/27/2012
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Primary Examiner(s): SONG, HUA JASMINE
• Application Number:
  US12/024,204
• Publication Number:
  US 20100293340A1
• Time in Patent Office: 1,516 Days
• Field of Search: 711/137, 711/146, 711/152, 711/154, 711/163, 711/E12.001, 711/E2.017, 712/207, 712/216, 712/220, 712/229
• US Class Current: 711/146
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

A wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism is configured to issue a look-ahead load command on a system bus to read a data value from a target address and perform a comparison operation to determine whether the data value at the target address indicates that an event for which a thread is waiting has occurred. In response to the comparison resulting in a determination that the event has not occurred, the wake-and-go engine populates a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity. In response to the comparison resulting in a determination that the event has occurred, the wake-and-go engine issues a load command on the system bus to read the data value from the target address with data exclusivity.

Claims

1. A method, in a data processing system, for performing a look-ahead operation in a wake-and-go mechanism, the method comprising:

responsive to the wake-and-go mechanism detecting a sequence of instructions in a thread that indicates the thread is waiting for an event associated with a target address, issuing a look-ahead load command on a system bus to read a data value from the target address;

performing a comparison operation to determine whether the data value at the target address indicates that the event for which the thread is waiting has occurred;

in response to the comparison resulting in a determination that the event has not occurred, populating a wake-and-go storage array with the target address and snooping the target address on the system bus without data exclusivity; and

in response to the comparison resulting in a determination that the event has occurred, issuing a load command on the system bus to read the data value from the target address with data exclusivity.

2. The method of claim 1, wherein the look-ahead load command is a load without reservation command.

3. The method of claim 1, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

4. The method of claim 1, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

5. The method of claim 4, wherein responsive to detecting the event, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

6. The method of claim 1, wherein the event is a direct memory access operation that moves data from a source address to the target address.

7. The method of claim 1, wherein issuing a load command on the system bus to read the data value from the target address with data exclusivity comprises issuing a load with reservation command on the system bus.

8. The method of claim 1, further comprising:

determining whether the wake-and-go engine obtains a lock for the target address; and

responsive to obtaining the lock for the target address, holding the lock for the thread.

9. The method of claim 8, further comprising:

responsive to a determination that the wake-and-go mechanism has not obtained the lock for the target address, placing an entry in the wake-and-go storage array to spin on the lock for the target address.

10. A data processing system, comprising:

a wake-and-go mechanism; and

awake-and-go storage array,

wherein the wake-and-go mechanism is configured to;

responsive to the wake-and-go mechanism detecting a sequence of instructions in a thread that indicates the thread is waiting for an event associated with a target address, issue a look-ahead load command on a system bus to read a data value from the target address;

perform a comparison operation to determine whether the data value at the target address indicates that the event for which the thread is waiting has occurred;

in response to the comparison resulting in a determination that the event has not occurred, populate a wake-and-go storage array with the target address and snoop the target address on the system bus without data exclusivity; and

in response to the comparison resulting in a determination that the event has occurred, issue a load command on the system bus to read the data value from the target address with data exclusivity.

11. The data processing system of claim 10, wherein the look-ahead load command is a load without reservation command.

12. The data processing system of claim 10, wherein the look-ahead load command is a specialized bus command indicating that the wake-and-go mechanism is performing a look-ahead polling operation without caching or data exclusivity.

13. The data processing system of claim 10, wherein the wake-and-go storage array is a content addressable memory and an address appearing on an address bus is used to address the content addressable memory.

14. The data processing system of claim 13, wherein responsive to detecting the event, the content addressable memory returns a storage address at which the target address is stored in the content addressable memory.

15. The data processing system of claim 10, wherein the event is a direct memory access operation that moves data from a source address to the target address.

16. The data processing system of claim 10, wherein issuing a load command on the system bus to read the data value from the target address with data exclusivity comprises issuing a load with reservation command on the system bus.

17. The data processing system of claim 10, wherein the wake-and-go mechanism is further configured to:

determine whether the wake-and-go engine obtains a lock for the target address; and

responsive to obtaining the lock for the target address, hold the lock for the thread.

18. The data processing system of claim 17, wherein the wake-and-go mechanism is further configured to:

responsive to a determination that the wake-and-go mechanism has not obtained the lock for the target address, place an entry in the wake-and-go storage array to spin on the lock for the target address.

19. A computer program product comprising a computer storage medium having a computer readable program stored thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

responsive to the wake-and-go mechanism detecting a sequence of instructions in a thread that indicates the thread is waiting for an event associated with a target address, issue a look-ahead load command on a system bus to read a data value from the target address;

perform a comparison operation to determine whether the data value at the target address indicates that the event for which the thread is waiting has occurred;

in response to the comparison resulting in a determination that the event has not occurred, populate a wake-and-go storage array with the target address and snoop the target address on the system bus without data exclusivity; and

in response to the comparison resulting in a determination that the event has occurred, issue a load command on the system bus to read the data value from the target address with data exclusivity.

20. The computer program product of claim 19, wherein the computer readable program further causes the computing device to:

determine whether the wake-and-go engine obtains a lock for the target address; and

responsive to a determination that the wake-and-go mechanism has not obtained the lock for the target address, place an entry in the wake-and-go storage array to spin on the lock for the target address.