Integrated device

• US 8,145,851 B2
• Filed: 09/06/2006
• Issued: 03/27/2012
• Est. Priority Date: 09/07/2005
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kashiwaya, Motofumi
• Primary Examiner(s): Peugh, Brian
• Assistant Examiner(s): SIMONETTI, NICHOLAS J
• Application Number:
  US11/515,886
• Publication Number:
  US 20070055917A1
• Time in Patent Office: 2,029 Days
• Field of Search: 711/5, 711147-150, 365/63, 365 66- 70, 365/51, 365/52, 365/230.03, 438/6, 438128-129
• US Class Current: 711/149
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An integrated device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access. An input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros. As connection interconnects, command information interconnects and data interconnects are included. The command information interconnects are formed by private interconnects, while the data interconnects are formed by private interconnects for at least the second direction interconnects.

Claims

1. An integrated device comprising:

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

wherein

each memory system includes a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects;

at least a portion of the data interconnects are formed by private interconnects; and

wherein memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

2. An integrated device as set forth in claim 1, wherein

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the memory macro therebetween;

and

the data interconnects are formed by private interconnects for at least the interconnects in the second direction.

3. An integrated device as set forth in claim 2, wherein

if a memory system is arranged to face the input/output ports, the first direction interconnects for the memory system are formed by private interconnects;

and

if a memory system is not arranged to face the input/output ports, the first direction interconnects of the data interconnects for a memory system are selectively formed by private interconnects or common interconnects in accordance with the interconnect resources.

4. An integrated device as set forth in claim 2, further comprising:

a sub processing module arranged at least one side of the region of the plurality of memory macros in the second direction, the sub processing modules being able to selectively access at least one of predetermined memory bank of the plurality of memory macros in the second direction; and

the data interconnects in the second direction able to be used as a second direction transfer mode.

5. An integrated device as set forth in claim 1, wherein

the device further includes a plurality of dies arranged at predetermined intervals;

and

the processing modules and the memory systems are formed at different dies.

6. An integrated device comprising:

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals, wherein

each memory system includes

a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro; and

wherein memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

7. An integrated device as set forth in claim 6, wherein

the plurality of dies are arranged to face each other;

a first die formed with the processing module includes the input/output port formed at its center; and

a second die formed with the memory system is formed with the memory interface at its center.

8. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

each memory system includes a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the plurality of access clusters are connected by buses;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects;

at least a portion of the data interconnects are formed by private interconnects; and

memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

9. An integrated device as set forth in claim 8, wherein, in each access cluster,

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the memory macro therebetween;

and

the plurality of access clusters are arranged in parallel in the second direction, and memory banks corresponding to the matrix arrangement of the plurality of memory macros are connected to each other by buses arranged in the second direction;

the data interconnects are formed by private interconnects for at least the interconnects in the second direction.

10. An integrated device as set forth in claim 9, wherein

if a memory system is arranged to face the input/output ports, the first direction interconnects for the memory system are formed by private interconnects;

and

if a memory system is not arranged to face the input/output ports, the first direction interconnects of the data interconnects for a memory system are selectively formed by private interconnects or common interconnects in accordance with the interconnect resources.

11. An integrated device as set forth in claim 10, further including a sub processing module arranged at least one side of the arrangement region of the plurality of memory macros in the second direction and able to selectively access a predetermined at least one memory bank of the plurality of memory macros in the second direction;

and

the data interconnects in the second direction able to be used as a second direction transfer mode.

12. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals;

each memory system includes

a memory macro having a boundary and including a plurality of memory banks and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the plurality of access clusters are connected by buses; and

wherein memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

13. An integrated device as set forth in claim 12, wherein

the plurality of dies are arranged to face each other,

a first die formed with the processing module includes the input/output port formed at its center;

and

a second die formed with the memory system is formed with the memory interface at its center.

14. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

each memory system includes

a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects; and

at least a portion of the data interconnects are formed by private interconnects;

the plurality of access clusters are symmetrically arranged in a predetermined direction via the interfaces and share memory interfaces arranged at corresponding positions with each other; and

memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

15. An integrated device as set forth in claim 14, wherein, in each access cluster,

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the memory macro therebetween;

and

the data interconnects are formed by private interconnects for at least the interconnects in the second direction; and

the plurality of access clusters are arranged symmetrically across the interface in the first direction and share memory interfaces arranged at positions corresponding with each other.

16. An integrated device as set forth in claim 15, wherein

if a memory system is arranged to face the input/output ports, the first direction interconnects for the memory system are formed by private interconnects;

and

if a memory system is not arranged to face the input/output ports, the first direction interconnects of the data interconnects for a memory system are selectively formed by private interconnects or common interconnects in accordance with the interconnect resources.

17. An integrated device as set forth in claim 16, wherein,

when the data interconnects are formed by private interconnects extending from the processing module up to the memory interface, the interconnects with respect to memory systems on the side exceeding the memory interface in the first direction are formed by a common interconnect;

and

the memory interface selectively transfers the data transferred through the private interconnects to the common interconnect interconnected in the first direction on the side exceeding the memory interface.

18. An integrated device as set forth in claim 17, wherein the memory interface selectively transfers the data transferred through the common interconnect to the private interconnects in the first direction on the side exceeding the memory interface.

19. An integrated device as set forth in claim 15, wherein

the shared memory interface includes an arbitration portion arbitrating the access to the desired memory system;

and

the arbitration portion selectively issues commands transmitted from the plurality of processing modules to the bank of at least one memory system between the memory system on the first side and the memory system on the second side arranged in the first direction sandwiching the memory interface therebetween.

20. An integrated device as set forth in claim 19, wherein the arbitration portion able to issue a plurality of commands to at least one of the memory system on the first side and the memory system on the second side.

21. An integrated device as set forth in claim 15, further including a sub processing module arranged at least one side of the arrangement region of the plurality of memory macros in the second direction and able to selectively access a predetermined at least one memory bank of the plurality of memory macros in the second direction;

and

the data interconnects in the second direction able to be used as a second direction transfer mode.

22. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals,

each memory system includes

a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the plurality of access clusters are symmetrically arranged in a predetermined direction via the interfaces and share memory interfaces arranged at corresponding positions with each other; and

wherein memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

23. An integrated device as set forth in claim 22, wherein

the plurality of dies are arranged to face each other;

a first die formed with the processing module includes the input/output port formed at its center; and

a second die formed with the memory system is formed with the memory interface at its center.

24. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port; and

a plurality of memory systems accessible by the processing module;

each memory system includes

a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the connection interconnects include instruction information interconnects and data interconnects being arranged in multiple layers;

the instruction information interconnects are formed by private interconnects; and

at least a portion of the data interconnects are formed by private interconnects;

the plurality of access clusters are symmetrically arranged in a first direction via the interfaces and share memory interfaces arranged at corresponding positions with each other;

a separate plurality of access clusters are arranged in parallel in a second direction substantially perpendicularly intersecting the first direction;

memory banks corresponding to the matrix form of the plurality of memory macros are connected to each other by buses arranged in the second direction; and

memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

25. An integrated device as set forth in claim 24, wherein, in each access cluster;

the memory interface is arranged such that the memory interface faces the processing module while sandwiching the memory macro therebetween;

and

the plurality of access clusters are arranged symmetrically across the interface in the first direction and share memory interfaces arranged at positions corresponding with each other; and

a separate plurality of access clusters are arranged in parallel in a second direction, and memory banks corresponding to the matrix form of the plurality of memory macros are connected to each other by buses arranged in the second direction.

26. An integrated device as set forth in claim 25, wherein,

when the data interconnects are formed by private interconnects extending from the processing module up to the memory interface, the interconnects with respect to memory systems on the side exceeding the memory interface in the first direction are formed by a common interconnect;

and

the memory interface selectively transfers the data transferred through the private interconnects to the common interconnect interconnected in the first direction on the side exceeding the memory interface.

27. An integrated device as set forth in claim 26, wherein the memory interface selectively transfers the data transferred through the common interconnect to the private interconnects in the first direction on the side exceeding the memory interface.

28. An integrated device as set forth in claim 25, wherein

the shared memory interface includes an arbitration portion arbitrating the access to the desired memory system;

and

the arbitration portion selectively issues commands transmitted from the plurality of processing modules to the bank of at least one memory system between the memory system on the first side and the memory system on the second side arranged in the first direction sandwiching the memory interface therebetween.

29. An integrated device as set forth in claim 28, wherein the arbitration portion able to issue a plurality of commands to at least one of the memory system on the first side and the memory system on the second side.

30. An integrated device as set forth in claim 25, further including a sub processing module arranged at least one side of the arrangement region of the plurality of memory macros in the second direction and able to selectively access a predetermined at least one memory bank of the plurality of memory macros in the second direction;

and

the data interconnects in the second direction able to be used as a second direction transfer mode.

31. An integrated device comprising:

a plurality of access clusters, wherein

each access cluster includes

at least one processing module including at least one input/output port;

a plurality of memory systems accessible by the processing module; and

a plurality of dies arranged at predetermined intervals;

each memory system includes

a memory macro having a boundary and including a plurality of memory banks; and

a memory interface connected to the processing module and each memory bank;

the processing module and the memory system are formed at different dies;

the input/output port of the processing module, each memory interface, and each memory bank are connected by connection interconnects, the interconnects being arranged in a first direction and a second direction so as to shape a matrix form within the boundary of the memory macro such that the processing module and each memory system is configured to interface and access each memory bank of the memory macro;

the plurality of access clusters are symmetrically arranged in the first direction via the interfaces and share memory interfaces arranged at corresponding positions with each other;

a separate plurality of access clusters are arranged in parallel in a second direction substantially perpendicularly intersecting the first direction;

memory banks corresponding to the matrix form of the plurality of memory macros are connected to each other by buses arranged in the second direction; and

wherein memory macros of the plurality of memory systems are arranged in parallel in the second direction, the second direction substantially perpendicularly intersecting the first direction, the first direction being a direction connecting the processing module and the memory interface.

32. An integrated device as set forth in claim 31, wherein

the plurality of dies are arranged to face each other;

a first die formed with the processing module includes the input/output port formed at its center; and

a second die formed with the memory system is formed with the memory interface at its center.