Reconfiguration of an accelerator module having a programmable logic device

• US 8,145,894 B1
• Filed: 02/24/2009
• Issued: 03/27/2012
• Est. Priority Date: 02/25/2008
• Status: Active Grant

• Current Assignee: DRC Computer
• Original Assignee: DRC Computer
• Inventors: Casselman, Steven Mark
• Primary Examiner(s): PATEL, NITIN C
• Application Number:
  US12/392,038
• Time in Patent Office: 1,127 Days
• Field of Search: 713/1, 713/2, 713/100
• US Class Current: 713/100
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS

Abstract

Reconfiguration of an accelerator module having a programmable logic device is described, where the reconfiguration is performed during runtime without rebooting. For example, a computer is put into a sleep mode, the computer having the accelerator module installed therein. A programmable logic device of the accelerator module is reconfigured while the computer is in the sleep mode.

Claims

1. A method for reconfiguration of an accelerator module, comprising:

putting a computer into a sleep mode, the computer having the accelerator module installed therein;

the accelerator module preconditioned to reconfigure a programmable logic device thereof responsive to assertion of a sleep mode command; and

reconfiguring the programmable logic device of the accelerator module while the computer is in the sleep mode.

2. The method according to claim 1, further comprising:

realigning a data path for synchronous communication from the accelerator module to a microprocessor of the computer, the data path having been previously aligned prior to the reconfiguring; and

reloading base and interrupt address information into the programmable logic device, the programmable logic device having been previously loaded with the base and interrupt address information prior to the reconfiguring.

3. The method according to claim 2, further comprising sending a realignment packet by the accelerator module to the microprocessor after exiting the sleep mode.

4. The method according to claim 2, further comprising sending a realignment packet by the accelerator module to the microprocessor prior to exiting the sleep mode.

5. The method according to claim 2, wherein:

the realigning is performed prior to exiting the sleep mode; and

the reloading is done after exiting the sleep mode.

6. The method according to claim 2, wherein the reloading is responsive to a driver call by a driver script associated with the accelerator module.

7. The method according to claim 6, wherein the base and interrupt address information is stored in system memory responsive to execution of the driver script.

8. The method according to claim 7, wherein the base and interrupt address information is stored in a kernel memory location in the system memory.

9. A method for reconfiguration of a programmable logic device, comprising:

coupling the programmable logic device to a first microprocessor socket for communication with a microprocessor coupled to a second microprocessor socket;

preconditioning the programmable logic device to reconfigure responsive to assertion of a sleep mode command; and

reconfiguring the programmable logic device at runtime while coupled to the first microprocessor socket while the microprocessor is in a sleep mode responsive to assertion of the sleep mode command.

10. The method according to claim 9, wherein the reconfiguration is performed after configuring the programmable logic device.

11. The method according to claim 10, wherein the reconfiguring is a partial reconfiguration of the programmable logic device after the configuring.

12. The method according to claim 11, wherein the first microprocessor socket and the second microprocessor socket are directly connected to one another for direct communication between the microprocessor and the programmable logic device.

13. A method for reconfiguring an accelerator module having a programmable logic device, comprising:

coupling the accelerator module to a central processing unit interface of a computer;

configuring programmable logic of the programmable logic device with a first configuration bitstream;

preconditioning the accelerator module to reconfigure the programmable logic responsive to assertion of a sleep mode command;

transitioning the computer from an operating state to a sleep mode responsive to assertion of the sleep mode command; and

reconfiguring the programmable logic of the programmable logic device during runtime of the computer with either the first configuration bitstream or a second configuration bitstream without having to reboot the computer between the configuring and the reconfiguring;

wherein the reconfiguring is performed while the computer is the sleep mode; and

exiting the sleep mode after completion of the reconfiguring.

14. The method according to claim 13, wherein the transitioning includes:

asserting the sleep mode command;

initiating a protocol to start the sleep mode;

sending a stop clock request from a hub to a microprocessor of the computer responsive to the sleep mode command;

sending the stop clock request to the accelerator module;

sending a stop clock grant from the microprocessor to the hub;

holding down a stop signal responsive to the stop clock grant; and

initiating the reconfiguring responsive to the sleep mode command.

15. The method according to claim 14, further comprising:

releasing the stop signal for the exiting of the sleep mode;

realigning a data path between the microprocessor and the accelerator module upon the exiting of the sleep mode; and

reloading interface information into the programmable logic device.

16. The method according to claim 13, further comprising:

bringing microprocessor interface links down in speed from an operational link status to a negotiation link status during the sleep mode;

wherein the reconfiguring includes instantiating a replacement reconfigurable processor system core in the programmable logic.

17. The method according to claim 13, wherein the reconfiguring is completed within a time window during the sleep mode.

18. A method for reconfiguration of an accelerator module coupled to a bus, comprising:

preconditioning the accelerator module to reconfigure programmable logic of the accelerator module responsive to assertion of a sleep mode command;

putting the bus into a sleep mode in response to assertion of the sleep mode command; and

reconfiguring programmable logic of the accelerator module while the bus is in the sleep mode.

19. The method according to claim 18, wherein the bus is for communication with a microprocessor via a bridge.

20. The method according to claim 18, wherein the bus is put into the sleep mode under control of a bridge.

21. The method according to claim 20, wherein the bus is a PCIe bus.

22. A method for reconfiguration, comprising:

providing an accelerator module coupled to a bus; and

providing a script for conditioning the accelerator module for reconfiguration during a sleep mode;

preconditioning the accelerator module to reconfigure programmable logic of the accelerator module responsive to assertion of a sleep mode command;

wherein the bus is put into the sleep mode responsive to assertion of the sleep mode command; and

wherein the programmable logic of the accelerator module is reconfigured while the bus is in the sleep mode.

23. The method according to claim 22, wherein the bus is for communication with a microprocessor via a bridge.

24. The method according to claim 22, wherein the bus is put into the sleep mode under control of a bridge.

25. The method according to claim 24, wherein the bus is a PCIe bus.