Integrated circuit fabrication process convergence

• US 8,146,023 B1
• Filed: 09/24/2009
• Issued: 03/27/2012
• Est. Priority Date: 10/02/2008
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Kumar, Bhavani P.
• Primary Examiner(s): Whitmore, Stacy
• Assistant Examiner(s): Dimyan, Magid
• Application Number:
  US12/565,787
• Time in Patent Office: 915 Days
• Field of Search: 716/136, 716/51
• US Class Current: 716/51
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for selecting a process for a new integrated circuit design. Structures that are used in existing integrated circuit designs are identified, as well as the photolithography processes that are used to fabricate integrated circuits that are based on the existing designs. A process window is determined for each structure/process combination by running tests on different combinations of process variables, and a database of the process windows is compiled. The structures that are to be used in the new integrated circuit design are identified, and the process windows associated with the identified structures for the new integrated circuit design are selected from the database. The selected process windows for the identified structures are overlaid, grouped by common process, thereby creating a resultant process window for each process. One of the processes is selected, based at least in part on comparative sizes of the resultant process windows.

Claims

1. A processor-based method for qualifying a process for a new integrated circuit design, the method comprising the steps of:

identifying structures that are used in existing integrated circuit designs,

identifying photolithography processes that are used to fabricate integrated circuits that are based on the existing designs,

determining a process window for each structure/process combination by running tests on different combinations of process variables,

compiling a database of the process windows,

identifying the structures that are to be used in the new integrated circuit design,

selecting from the database the process windows associated with the identified structures for the new integrated circuit design,

using the processor, overlaying the selected process windows for the identified structures, grouped by common process, thereby creating a resultant process window for each process, and

selecting one of the processes based at least in part on comparative sizes of the resultant process windows.

2. The method of claim 1, further comprising the step of confirming the selected process by running tests on the new integrated circuit design using process parameters based at least in part on the resultant process window.

3. The method of claim 1, further comprising selecting as a monitor structure the structure associated with the process window that most limits a size of the resultant process window.

4. The method of claim 1, wherein the process variables comprise exposure and focus.

5. A processor-based method for qualifying a process for a new integrated circuit design, the method comprising the steps of:

identifying the structures that are to be used in the new integrated circuit design,

selecting process windows associated with the identified structures for the new integrated circuit design from a database of process windows for structure/process combinations,

using the processor, overlaying the selected process windows for the identified structures, grouped by common process, thereby creating a resultant process window for each process, and

selecting one of the processes based at least in part on comparative sizes of the resultant process windows.

6. The method of claim 5, further comprising the step of confirming the selected process by running tests on the new integrated circuit design using process parameters based at least in part on the resultant process window.

7. The method of claim 5, further comprising selecting as a monitor structure the structure associated with the process window that most limits a size of the resultant process window.

8. The method of claim 5, wherein process variables for the process windows comprise exposure and focus.