Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs
First Claim
1. A method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising:
- receiving a 3D-IC die description which describes the 3D-IC die, wherein the 3D-IC die comprises two or more vertically stacked 2D-IC dies which are coupled through at least one through-silicon via (TSV);
transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description and wherein the set of 2D-IC die descriptions includes a modified TSV;
for each 2D-IC die description in the set of 2D-IC die descriptions, performing, by computer, an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and
combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.
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Abstract
One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.
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Citations
29 Claims
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1. A method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising:
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receiving a 3D-IC die description which describes the 3D-IC die, wherein the 3D-IC die comprises two or more vertically stacked 2D-IC dies which are coupled through at least one through-silicon via (TSV); transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description and wherein the set of 2D-IC die descriptions includes a modified TSV; for each 2D-IC die description in the set of 2D-IC die descriptions, performing, by computer, an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for performing an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, the method comprising:
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receiving a 3D-IC die description which describes the 3D-IC die, wherein the 3D-IC die comprises two or more vertically stacked 2D-IC dies which are coupled through at least one through-silicon via (TSV); transforming the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description and wherein the set of 2D-IC die descriptions includes a modified TSV; for each 2D-IC die description in the set of 2D-IC die descriptions, performing an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file; and combining the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. An apparatus that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die, comprising:
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a processor; a memory; a receiving mechanism configured to receive a 3D-IC die description which describes the 3D-IC die, wherein the 3D-IC die comprises two or more vertically stacked 2D-IC dies which are coupled through at least one through-silicon via (TSV); a transforming mechanism configured to transform the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description and wherein the set of 2D-IC die descriptions includes a modified TSV; a 2D-IC extraction tool configured to perform an electrical property extraction for each 2D-IC die description in the set of 2D-IC die descriptions to obtain a 2D-IC RLC netlist file; and a combining mechanism configured to combine the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.
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Specification