Insulated gate type semiconductor device and method for fabricating the same

• US 8,148,224 B2
• Filed: 09/23/2011
• Issued: 04/03/2012
• Est. Priority Date: 02/19/2001
• Status: Expired due to Term

• Current Assignee: Renesas Semiconductor Package & Test Solutions Co., Ltd. (Renesas Electronics Corporation)
• Original Assignee: Hitachi TOBU Semiconductor Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Inagawa, Hiroshi, Machida, Nobuo, Oishi, Kentaro
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US13/243,756
• Publication Number:
  US 20120015492A1
• Time in Patent Office: 193 Days
• Field of Search: 438/135, 438/138, 257/E21.384
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Claims

1. A method of manufacturing a semiconductor device including a MISFET, comprising the steps of:

(a) providing a semiconductor substrate of a first conductivity type;

(b) forming a first trench in the semiconductor substrate;

(c) forming a first conductive film in the first trench, wherein the first conductive film has a protruding portion which protrudes from a surface of the semiconductor substrate;

(d) forming a first impurity region of a second conductivity type opposite the first conductivity type in the semiconductor substrate, wherein a depth of the first impurity region is shallower than a depth of the first trench;

(e) forming a second impurity region of the first conductivity type in the semiconductor substrate, wherein a depth of the second impurity region is shallower than the depth of the first impurity region;

(f) forming a side wall spacer over the second impurity region and over a side surface of the protruding portion;

(g) forming a second trench by using the side wall spacer as a mask in the semiconductor substrate, wherein the second trench penetrates the second impurity region and reaches the first semiconductor impurity region;

(h) forming a third impurity region of the second conductivity type in the first impurity region located at a bottom of the second trench, wherein an impurity concentration of the third impurity region is higher than an impurity concentration of the first impurity region;

(i) after the step (h), recessing the side wall spacer, thereby a part of a surface of the second impurity region is exposed; and

(j) after the step (i), forming a second conductive film in the second trench, wherein the conductive film is electrically connected with the exposed surface of the second impurity region outside of the second trench and is electrically connected with the first, second and third impurity regions inside of the second trench.

2. A method of manufacturing a semiconductor device according to claim 1,

wherein the first conductive film constitutes a gate electrode of the MISFET,

wherein the first impurity region constitutes a channel region of the MISFET,

wherein the second impurity region constitutes a source region of the MISFET, and

wherein the semiconductor substrate constitutes a drain region of the MISFET.

3. A method of manufacturing a semiconductor device according to claim 1,

wherein a cap film is formed over a top surface of the first conductive film.

4. A method of manufacturing a semiconductor device according to claim 1,

wherein the first conductive film is made of a poly-silicon film.

5. A method of manufacturing a semiconductor device according to claim 1,

wherein the first conductive type is n-type, and

wherein the second conductive type is p-type.

6. A method of manufacturing a semiconductor device according to claim 1,

wherein the side wall spacer is made of a silicon oxide film.

7. A method of manufacturing a semiconductor device according to claim 1,

wherein a height of the side wall spacer is higher than a height of the first conductive film.

8. A method of manufacturing a semiconductor device including a MISFET, comprising the steps of:

(a) providing a semiconductor substrate of n-type;

(b) forming a first trench in the semiconductor substrate;

(c) forming a first conductive film as a gate electrode of the MISFET in the first trench, wherein the first conductive film has a protruding portion which protrudes from a surface of the semiconductor substrate;

(d) forming a first impurity region of p-type as a channel region of the MISFET in the semiconductor substrate, wherein a depth of the first impurity region is shallower than a depth of the first trench;

(e) forming a second impurity region of n-type as a source region of the MISFET in the semiconductor substrate, wherein a depth of the second impurity region is shallower than the depth of the first impurity region;

(f) forming a side wall spacer made of an insulating film over the second impurity region and over a side surface of the protruding portion;

(g) forming a second trench by using the side wall spacer as a mask in the semiconductor substrate, wherein the second trench penetrates the second impurity region and reaches the first semiconductor impurity region;

(h) forming a third impurity region of p-type in the first impurity region located at a bottom of the second trench, wherein an impurity concentration of the third impurity region is higher than an impurity concentration of the first impurity region;

(i) after the step (h), recessing the side wall spacer, thereby a part of a surface of the second impurity region is exposed; and

(j) after the step (i), forming a second conductive film in the second trench, wherein the conductive film is electrically connected with the exposed surface of the second impurity region outside of the second trench and is electrically connected with the first, second and third impurity regions inside of the second trench.

9. A method of manufacturing a semiconductor device according to claim 8,

wherein a cap film is formed over a top surface of the first conductive film.

10. A method of manufacturing a semiconductor device according to claim 8, wherein the first conductive film is made of a poly-silicon film.

11. A method of manufacturing a semiconductor device according to claim 8,

wherein the side wall spacer is made of a silicon oxide film.

12. A method of manufacturing a semiconductor device according to claim 8,

wherein a height of the side wall spacer is higher than a height of the first conductive film.