Semiconductor power device having a top-side drain using a sinker trench

• US 8,148,233 B2
• Filed: 07/07/2011
• Issued: 04/03/2012
• Est. Priority Date: 08/03/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E., Dolny, Gary M.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/178,391
• Publication Number:
  US 20110260241A1
• Time in Patent Office: 271 Days
• Field of Search: 257328-333, 257/335, 257/339, 257/341, 257/401, 438135-138, 438/173, 438/243
• US Class Current: 438/401
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches. The plurality of stripe-shaped sinker trenches extend from a top surface of the silicon region through the silicon region and terminate within the substrate. The plurality of stripe-shaped sinker trenches are lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer along the top of the sinker trench.

Claims

1. A semiconductor power device comprising:

a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate; and

a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of stripe-shaped gate trenches, the plurality of stripe-shaped sinker trenches extending from a top surface of the silicon region through the silicon region and terminating within the substrate, the plurality of stripe-shaped sinker trenches being lined with an insulator along the sinker trench sidewalls so that a conductive material filling each sinker trench makes electrical contact with the substrate along the bottom of the sinker trench and makes electrical contact with an interconnect layer, wherein the plurality of sinker trenches are wider and extend deeper than the plurality of groups of stripe-shape gate trenches.

2. The semiconductor power device of claim 1 wherein the silicon region is an epitaxial layer, the semiconductor power device further comprising:

a well region of a second conductivity type abutting each gate trench, the well regions extending in the epitaxial layer;

source regions of a first conductivity type in the well regions, the source regions flanking the plurality of groups of stripe-shaped gate trenches;

a gate dielectric layer lining at least the sidewalls of each gate trench; and

a gate electrode at least partially filling each gate trench,

wherein a gate electrode contact layer electrically contacting the gate electrodes, a source contact layer electrically contacting the source regions, and a drain contact layer electrically contacting the substrate are all along one surface of the semiconductor power device.

3. The semiconductor power device of claim 1 wherein the conductive material includes one or more of doped polysilicon, selective epitaxial silicon (SEG), metal, and metallic compound.

4. The semiconductor power device of claim 1 wherein the interconnect layer electrically connects the conductive material filling each of the plurality of stripe-shaped sinker trenches to a drain pad configured to receive a drain bond-wire.

5. The semiconductor power device of claim 1 wherein the insulator comprises one of oxide, silicon nitride, silicon oxynitride, multilayer of oxide and nitride, a low k insulating material, and a high k insulating material.

6. The semiconductor power device of claim 1 further comprising a back-side metal layer extending along a bottom surface of the substrate.

7. The semiconductor power device of claim 1 wherein the conductive material comprises polysilicon and a ratio of a width of each sinker trench to a width of each gate trench is less than five to one.

8. The semiconductor power device of claim 1 wherein the conductive material comprises a metal and a ratio of a width of each sinker trench to a width of each gate trench is less than three to one.

9. The semiconductor power device of claim 2 wherein the insulator lining the sidewalls of the plurality of sinker trenches is thicker than the gate dielectric layer.

10. The semiconductor power device of claim 2 wherein the insulator lining the sidewalls of the plurality of sinker trenches and the gate dielectric layer have the same thickness.

11. The semiconductor power device of claim 2 wherein each gate trench further includes a thick bottom dielectric below the gate electrode, the thick bottom dielectric having a greater thickness than that of the gate dielectric.

12. The semiconductor power device of claim 2 wherein each gate trench includes a shield electrode below the gate electrode, the gate and shield electrodes being insulated from one another.

13. The semiconductor power device of claim 2 wherein the plurality of the sinker trenches are laterally spaced from corresponding groups of gate trenches, with no well regions abutting sidewalls of the plurality of sinker trenches.

14. The semiconductor power device of claim 1 wherein the interconnect layer makes electrical contact with the conductive material along the top of each sinker trench.