Solid state charge qubit device

• US 8,148,715 B2
• Filed: 02/19/2010
• Issued: 04/03/2012
• Est. Priority Date: 08/20/2002
• Status: Active Grant

• Current Assignee: NewSouth Innovations Pty Limited (University Of New South Wales)
• Original Assignee: Quocor Pty., Ltd.
• Inventors: Hollenberg, Lloyd Christopher Leonard, Dzurak, Andrew Steven, Wellard, Cameron, Hamilton, Alexander Rudolf, Reilly, David J., Milburn, Gerard J., Clark, Robert Graham
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US12/660,085
• Publication Number:
  US 20110049475A1
• Time in Patent Office: 774 Days
• Field of Search: 257/9, 257/14, 257/24, 257/288, 257/E29.168, 257/E45.005, 257/E49.003, 977/933
• US Class Current: 257/14
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06N 10/00 Quantum computing, i.e. information processing based on quantum-mechanical phenomena
• CPC Class Codes: Y10S 977/933 Spintronics or quantum computing

Abstract

This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Claims

1. A quantum device, comprising:

an electrically inert solid semiconductor substrate within which there is;

a charge qubit comprising a pair of dopant atoms having a net charge and an electric field having two potential wells, wherein the two potential wells are located adjacent respective dopant atoms;

and wherein a location of the net charge in the electric field having two potential wells defines a logical state of the charge qubit;

and wherein a first gate is located over a potential barrier between the two potential wells to control a barrier height; and

at least one second gate is located to control relative shapes and sizes of the two potential wells, wherein the semiconductor substrate and the dopant atoms are selected to create a system equivalent to an artificial H₂⁺ molecule.

2. A quantum device according to claim 1, wherein the logical state of the charge qubit is defined by a the location of a single electron in one of the two potential wells.

3. A quantum device according to claim 1, wherein the logical state of the charge qubit is defined by lowest symmetric or antisymmetric molecular states.

4. A quantum device according to claim 1, wherein spacing between the dopant atoms is up to 200 nm.

5. A quantum device according to claim 4, wherein the spacing between the dopant atoms is in a the range of 20 to 100 nm.

6. A quantum device according to claim 1, wherein the two dopant atoms are buried in the substrate to a depth up to 200 nm.

7. A quantum device according to claim 6, wherein the two dopant atoms are buried in the substrate to a depth in a range of 5 to 50 nm.

8. A quantum device according to claim 1, wherein the semiconductor substrate is coated with an insulating layer.

9. A quantum device according to claim 8, wherein the insulating layer is SiO₂.

10. A quantum device according to claim 1, wherein gate electrodes are placed on a surface of the substrate above the dopant atoms to allow for external control of charge wavefunctions, wherein the first gate is a ‘

barrier’

gate or B-gate.

11. A quantum device according to claim 10, wherein the at least one second gate is a ‘

potential off-set’

, ‘

symmetry’

or S-gate.

12. A quantum device according to claim 11, wherein suitable biasing of the first and second gates allows one qubit logic operation to be performed.

13. A quantum device according to claim 9, wherein one or more charge detection devices are provided on a surface of the substrate for charge qubit readout and to confirm initialization of the charge qubit.

14. A quantum device according to claim 13, wherein the one or more charge detection devices is a sensitive field-effect transistor or a single electron transistor (SET).

15. A quantum device according to claim 1, wherein a configuration comprising two dopant atoms, surface gates and surface charge detection devices is repeated many times on a single silicon chip, allowing for scale-up to a many charge qubit processor.

16. A quantum device according to claim 15, wherein the device is cooled to ensure that the dopant atoms are not thermally ionized and to minimize coupling of the charge qubits to an environment.

17. A quantum device according to claim 16, wherein the device is cooled to 4K or below.