Semiconductor device having an element mounted on a substrate and an electrical component connected to the element

• US 8,148,738 B2
• Filed: 06/15/2007
• Issued: 04/03/2012
• Est. Priority Date: 06/16/2006
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Murayama, Kei, Higashi, Mitsutoshi, Koizumi, Naoyuki, Taguchi, Yuichi, Shiraishi, Akinori, Sunohara, Masahiro
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Ingham, John C
• Application Number:
  US11/812,149
• Publication Number:
  US 20070290329A1
• Time in Patent Office: 1,754 Days
• Field of Search: 257/84, 257/93, 257/E25.032
• US Class Current: 257/84
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/4823 connecting the wire to a pin of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/4926 the materials containing semiconductor material
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12035 Zener diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In a semiconductor device 100, a light emitting element 120 has been mounted on an upper plane of a semiconductor substrate 102. In an impurity diffusion region of the semiconductor substrate 102, a P conducting type of a layer 104, and an N layer 106 have been formed, while an N conducting type impurity is implanted to the P layer 104, and then the implanted impurity is diffused to constitute the N layer 106. A zener diode 108 made of a semiconductor device has been formed by the P layer 104 and the N layer 106.

Claims

1. A semiconductor device comprising:

a substrate, the substrate including,

a first wiring layer, and

a second wiring layer;

an electronic component;

a first electrode connected to the electronic component;

a second electrode connected to the electronic component;

a first coupling between the first electrode and the first wiring layer; and

a second coupling between the second electrode and the second wiring layer,

wherein

the substrate is a semiconductor substrate;

a region of a semiconductor element formed in an impurity diffusion region of the semiconductor substrate is electrically connected to the electronic component;

a plurality of penetration electrodes, which are electrically connected to the electronic component, formed in the semiconductor substrate, the plurality of penetration electrodes including a first penetration electrode and a second penetration electrode, with the first penetration electrode being connected to the first wiring layer and the second penetration electrode being connected to the second wiring layer;

the first wiring layer which is formed on a surface of the semiconductor substrate facing the electronic component and over the first penetration electrode, and which connects a first region of the semiconductor element to the first penetration electrode and the first electrode of the electronic component,

the second wiring layer which is formed on the surface of the semiconductor substrate facing the electronic component and over the second penetration electrode, and which connects a second region of the semiconductor element to the second penetration electrode and the second electrode of the electronic component; and

a protection film formed on an entire surface of the semiconductor substrate, including on an inner wall of a hole in the semiconductor substrate, such that the first wiring layer, the second wiring layer, the first penetration electrode and the second penetration electrode are formed on the semiconductor substrate via the protection film,

wherein the first wiring layer is connected to the first region of the semiconductor element via a first connecting portion, wherein the first connecting portion is formed in the protection film formed on the surface of the semiconductor substrate facing the electronic component,

wherein the second wiring layer is connected to the second region of the semiconductor element via a second connecting portion, wherein the second connecting portion is formed in the protection film formed on the surface of the semiconductor substrate facing the electronic component,

wherein the first penetration electrode is opposed to the first electrode, and

wherein the second penetration electrode is opposed to the second electrode.

2. The semiconductor device as claimed in claim 1, wherein

the semiconductor element is formed by at least two regions having different conductivity types.

3. The semiconductor device as claimed in claim 1, wherein

the semiconductor element is a zener diode capable of avoiding a voltage higher or equal to a predetermined voltage applied to the electronic component.

4. The semiconductor device as claimed in claim 1, wherein the first penetration electrode is connected to a third wiring layer formed on a second surface opposite the surface of the semiconductor substrate facing the electronic component, and the second penetration electrode is connected to a fourth wiring layer formed on the second surface opposite the surface of the semiconductor substrate facing the electronic component.

5. The semiconductor device as claimed in claim 1, wherein

the semiconductor substrate is a silicon substrate.

6. The semiconductor device as claimed in claim 1, wherein

the electronic component is sealed on the substrate by a sealing structural member provided with an optical transmitting plane having an optical transmitting characteristic.

7. The semiconductor device as claimed in claim 1, further comprising:

a third penetration electrode; and

a third electrode connected to the electronic component,

wherein the third penetration electrode is connected to the third electrode of the electronic component and the first region of the semiconductor element via the first wiring layer.

8. The semiconductor device as claimed in claim 1, wherein the protection film includes an insulating film.

9. A substrate, comprising:

a semiconductor element formed by a first region and a second region which have different conductivity types;

a first penetration electrode electrically connected to the first region of the semiconductor element;

a second penetration electrode electrically connected to the second region of the semiconductor element;

a first wiring layer which is formed on a surface of the substrate adapted to face an electronic component and over the first penetration electrode, and which connects the first region of the semiconductor element to the first penetration electrode and a first electrode connected to the electronic component,

a second wiring layer which is formed on the surface of the substrate adapted to face the electronic component and over the second penetration electrode, and which connects the second region of the semiconductor element to the second penetration electrode and a second electrode connected to the electronic component; and

a protection film formed on an entire surface of the substrate, including on an inner wall of a hole in the substrate, such that the first wiring layer, the second wiring layer, the first penetration electrode and the second penetration electrode are formed on the substrate via the protection film,

wherein the first wiring layer is connected to the first region of the semiconductor element via a first connecting portion, wherein the first connecting portion is formed in the protection film formed on the surface of the semiconductor substrate adapted to face the electronic component,

wherein the second wiring layer is connected to the second region of the semiconductor element via a second connecting portion, wherein the second connecting portion is formed in the protection film formed on the surface of the semiconductor substrate adapted to face the electronic component,

wherein the first penetration electrode is opposed to the first electrode, and

wherein the second penetration electrode is opposed to the second electrode.

10. The substrate as claimed in claim 9, wherein the first penetration electrode is connected to a third wiring layer formed on a second surface opposite the surface of the substrate adapted to face the electronic component, and the second penetration electrode is connected to a fourth wiring layer formed on the second surface opposite the surface of the substrate adapted to face the electronic component.

11. The substrate as claimed in claim 9, further comprising

a third penetration electrode;

and

a third electrode connected to the electronic component,

wherein the third penetration electrode is connected to the third electrode and the first region of the semiconductor element via the first wiring layer.

12. The substrate as claimed in claim 9, wherein the protection film includes an insulating film.