Trench-shielded semiconductor device

• US 8,148,749 B2
• Filed: 02/19/2009
• Issued: 04/03/2012
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Grebs, Thomas E., Rinehimer, Mark, Yedinak, Joseph, Probst, Dean E., Dolny, Gary, Benjamin, John
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US12/389,335
• Publication Number:
  US 20100207205A1
• Time in Patent Office: 1,139 Days
• Field of Search: None
• US Class Current: 257/172
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of a first conductivity type disposed in the semiconductor region and around the first area, and a plurality of trenches extending in a semiconductor region. Each trench haves a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area. Each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

Claims

1. A semiconductor device comprising:

a semiconductor region having a surface;

a first area of the semiconductor region;

a well region of a first conductivity type disposed in the semiconductor region and around the first area, the semiconductor region having a second conductivity type that is opposite to the first conductivity type, the well region having a bottom surface disposed below the surface of the semiconductor region; and

a plurality of trenches extending in a semiconductor region, each trench having a first end disposed in a first portion of the well region and above the bottom surface of the well region, a second end disposed in a second portion of the well region and above the bottom surface of the well region, and a middle portion between the first and second ends and disposed in the first area, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer.

2. The semiconductor device of claim 1, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench.

3. The semiconductor device of claim 1, wherein the trenches are disposed parallel to one another.

4. The semiconductor device of claim 3, further comprising a first end trench disposed in the well region, the first end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the first end trench being further disposed to one side of the plurality of trenches and parallel to the plurality of trenches.

5. The semiconductor device of claim 4, wherein the first end trench has a width that is in the range of 0.8 times to 1.2 times the width of a trench of the plurality of trenches.

6. The semiconductor device of claim 4, further comprising a first mesa disposed between two adjacent trenches of the plurality of trenches, and a second mesa disposed between the first end trench and the plurality of trenches, wherein the second mesa has a width that is in the range of 0.8 times to 1.2 times the width of a trench of the first mesa.

7. The semiconductor device of claim 4, further comprising a second end trench disposed in the well region, the second end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the second end trench being further disposed perpendicular to the first ends of the plurality of trenches.

8. The semiconductor device of claim 7, wherein the first ends of the first and second end trenches are joined together.

9. The semiconductor device of claim 8, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench, and wherein the bottoms of the first and second end trenches lie below the bottom of the middle portion of at least one of the other trenches.

10. The semiconductor device of claim 3, further comprising an end trench disposed in the well region, the end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the end trench being further disposed perpendicular to the first ends of the plurality of trenches.

11. The semiconductor device of claim 1, further comprising a perimeter trench disposed in the well region and encircling the plurality of trenches.

12. The semiconductor device of claim 1, further comprising an active region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor region and within the first area thereof.

13. The semiconductor device of claim 1, wherein the well region has a surface that is flush with the surface of the semiconductor region.

14. A semiconductor device comprising:

a semiconductor region having a surface; and

a plurality of trenches extending in a semiconductor region, each trench having a first end, a second end, and a middle portion between the first and second ends, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, wherein the conductive electrode comprises p-doped polysilicon, wherein at least a portion of the p-doped polysilicon has a net doping level of 1×

10¹⁸ dopant atoms per cubic centimeter (cm<sup>−

3</sup>) or higher.

15. A method of manufacturing a semiconductor device with one or more trenches, the method comprising:

forming one or more trenches extending into a semiconductor region, the semiconductor region having a surface, each trench having a first end, a second end, and a middle portion between the first and second ends, each trench further having a bottom wall opposing side walls, the one or more trenches defining surfaces of the semiconductor region that are adjacent to the one or more trenches;

forming a dielectric layer on the side and bottom walls of the one or more trenches; and

filling the one or more trenches with p-doped polysilicon material to provide conductive electrodes, wherein the p-doped polysilicon material is disposed on at least a portion of the dielectric material of each trench, wherein at least a portion of the p-doped polysilicon has a net doping level of 1×

10¹⁸ dopant atoms per cubic centimeter (cm<sup>−

3</sup>) or higher.

16. The method of claim 15, wherein forming the dielectric layer forms the layer on the surfaces of the semiconductor region that are adjacent to the one or more trenches;

and wherein filling the one or more trenches with p-doped polysilicon material comprises;

depositing a layer of p-doped polysilicon material over the dielectric layer;

annealing the deposited polysilicon material; and

removing a top portion of the annealed polysilicon material.

17. The method of claim 16, wherein the polysilicon material is deposited at a first temperature, and wherein annealing the deposited polysilicon material comprises heating the deposited polysilicon layer to a second temperature that is greater than the first temperature.

18. The method of claim 15, wherein filling the one or more trenches with p-doped polysilicon material comprises:

depositing a layer of polysilicon material over the dielectric layer and semiconductor region;

implanting a p-type dopant into the polysilicon material;

annealing the implanted polysilicon material; and

removing a top portion of the annealed polysilicon material.

19. The method of claim 18, wherein implanting a p-type dopant comprises implanting the dopant at two or more implant energy levels.

20. The method of claim 18 wherein the implanted dose of the p-type dopant is at least 5×

10¹⁴ dopant atoms per square centimeter.

21. The method of claim 18 wherein the implanted dose of the p-type dopant is in the range of 5×

10¹⁴ dopant atoms per square centimeter to 5×

10¹⁶ dopant atoms per square centimeter.

22. The method of claim 15, wherein forming the dielectric layer forms the layer on the surfaces of the semiconductor region that are adjacent to the one or more trenches;

and wherein filling the one or more trenches with p-doped polysilicon material comprises;

depositing a layer of polysilicon material over the dielectric layer;

annealing the polysilicon material while exposing the polysilicon material to a vapor-phase p-type dopant; and

removing a top portion of the annealed polysilicon material.

23. A semiconductor device comprising:

a semiconductor region having a surface;

a first area of the semiconductor region;

a well region of a first conductivity type disposed in the semiconductor region and around the first area; and

a plurality of trenches extending in a semiconductor region and disposed parallel to one another, each trench having a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer;

a first end trench disposed in the well region, the first end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the first end trench being further disposed to one side of the plurality of trenches and parallel to the plurality of trenches; and

a second end trench disposed in the well region, the second end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the second end trench being further disposed perpendicular to the first ends of the plurality of trenches.

24. The semiconductor device of claim 23, wherein the first ends of the first and second end trenches are joined together.

25. The semiconductor device of claim 24, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench, and wherein the bottoms of the first and second end trenches lie below the bottom of the middle portion of at least one of the other trenches.

26. A semiconductor device comprising:

a semiconductor region having a surface;

a first area of the semiconductor region;

a well region of a first conductivity type disposed in the semiconductor region and around the first area;

a plurality of trenches extending in a semiconductor region and disposed parallel to one another, each trench having a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer; and

an end trench disposed in the well region, the end trench having a first end, a second end, opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer, the end trench being further disposed perpendicular to the first ends of the plurality of trenches.

27. The semiconductor device of claim 26, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench.

28. The semiconductor device of claim 26, further comprising an active region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor region and within the first area thereof.

29. The semiconductor device of claim 26, wherein the well region has a surface that is flush with the surface of the semiconductor region.

30. A semiconductor device comprising:

a semiconductor region having a surface;

a first area of the semiconductor region;

a well region of a first conductivity type disposed in the semiconductor region and around the first area;

a plurality of trenches extending in a semiconductor region, each trench having a first end disposed in a first portion of the well region, a second end disposed in a second portion of the well region, and a middle portion between the first and second ends and disposed in the first area, each trench further having opposing sidewalls lined with a dielectric layer, and a conductive electrode disposed on at least a portion of the dielectric layer; and

a perimeter trench disposed in the well region and encircling the plurality of trenches.

31. The semiconductor device of claim 30, wherein at least a portion of the well region has a surface that is recessed below the surface of the semiconductor region, and wherein the bottoms of the first and second end portions of each trench lies below the bottom of the middle portion of the trench.

32. The semiconductor device of claim 30, wherein the trenches are disposed parallel to one another.

33. The semiconductor device of claim 30, further comprising an active region of a second conductivity type opposite to the first conductivity type disposed in the semiconductor region and within the first area thereof.

34. The semiconductor device of claim 30, wherein the well region has a surface that is flush with the surface of the semiconductor region.