Recessed channel array transistor (RCAT) structures

• US 8,148,772 B2
• Filed: 01/31/2011
• Issued: 04/03/2012
• Est. Priority Date: 05/30/2008
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doyle, Brian S., Pillarisetty, Ravi, Dewey, Gilbert, Chau, Robert S.
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/017,309
• Publication Number:
  US 20110121385A1
• Time in Patent Office: 428 Days
• Field of Search: 257/327, 257/407, 257/E21.615, 257/E29.264, 438/289, 438/589
• US Class Current: 257/327
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Recessed channel array transistor (RCAT) structures and method of formation are generally described. In one example, an electronic device includes a semiconductor substrate, a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region, and a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region, wherein the first gate structure is formed by removing a sacrificial gate structure to expose the first fin in the first gate region, recessing a channel structure into the first fin, and forming the first gate structure on the recessed channel structure.

Claims

1. An apparatus, comprising:

a semiconductor substrate;

a first fin coupled with the semiconductor substrate, the first fin comprising a first source region and a first drain region;

a first gate structure of a recessed channel array transistor (RCAT) formed in a first gate region disposed between the first source region and the first drain region;

a second fin coupled with the semiconductor substrate, the second fin comprising a second source region, a second drain region, and a second gate region wherein the second gate region is disposed between the second source region and the second drain region; and

a second gate structure of a multi-gate transistor formed on the second gate region of the second fin wherein the multi-gate transistor comprises a logic device and wherein the RCAT comprises a memory device.

2. An apparatus according to claim 1, wherein the first gate structure of the RCAT comprises a first gate width, and wherein the second gate structure of the multi-gate transistor comprises a second gate width, wherein the first gate width is greater than about two times the second gate width.

3. An apparatus according to claim 1, wherein the first gate structure of the RCAT is further formed by recessing the channel structure to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor.

4. An apparatus according to claim 1, wherein the RCAT comprises a first gate leakage current and the multi-gate transistor comprises a second gate leakage current, wherein the first gate leakage current is less than about one thousand times smaller than the second gate leakage current.

5. An apparatus according to claim 1, wherein the semiconductor substrate comprises silicon, the recessed channel structure comprises silicon, and wherein the first gate structure comprises:

a gate dielectric coupled with the recessed channel structure, the gate dielectric comprising a dielectric constant, k, greater than about 4; and

a gate electrode coupled with the gate dielectric, the gate electrode comprising a bandgap energy between about 4.1 electron volts (eV) and about 4.9 eV.

6. An apparatus according to claim 1, further comprising:

a dielectric material coupled with the first source region and the first drain region of the first fin and also coupled with the semiconductor substrate, the recessed channel structure, and the first gate structure.

7. An apparatus according to claim 2, wherein the first gate structure of the RCAT is further formed by recessing the channel structure to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor.

8. An apparatus according to claim 7, wherein the RCAT comprises a first gate leakage current and the multi-gate transistor comprises a second gate leakage current, wherein the first gate leakage current is less than about one thousand times smaller than the second gate leakage current.

9. An apparatus according to claim 5, wherein the first gate structure of the RCAT comprises a first gate width, and wherein the second gate structure of the multi-gate transistor comprises a second gate width, wherein the first gate width is greater than about two times the second gate width.

10. An apparatus according to claim 9, wherein the first gate structure of the RCAT is further formed by recessing the channel structure to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor.

11. An apparatus according to claim 10, wherein the RCAT comprises a first gate leakage current and the multi-gate transistor comprises a second gate leakage current, wherein the first gate leakage current is less than about one thousand times smaller than the second gate leakage current.

12. An apparatus according to claim 6, wherein the first gate structure of the RCAT comprises a first gate width, and wherein the second gate structure of the multi-gate transistor comprises a second gate width, wherein the first gate width is greater than about two times the second gate width.

13. An apparatus according to claim 12, wherein the first gate structure of the RCAT is further formed by recessing the channel structure to a depth that is between about half to about four times the drawn gate length of the second gate structure of the multi-gate transistor.

14. An apparatus according to claim 13, wherein the RCAT comprises a first gate leakage current and the multi-gate transistor comprises a second gate leakage current, wherein the first gate leakage current is less than about one thousand times smaller than the second gate leakage current.