Method and structures of monolithically integrated ESD suppression device

• US 8,148,781 B2
• Filed: 07/28/2009
• Issued: 04/03/2012
• Est. Priority Date: 07/28/2008
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao (Charles)
• Primary Examiner(s): Nguyen, Cuong Q
• Application Number:
  US12/511,002
• Publication Number:
  US 20100187652A1
• Time in Patent Office: 980 Days
• Field of Search: 257355-363, 257/E27.06, 257/E29.255
• US Class Current: 257/355
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs.

Claims

1. An electrostatic discharge device for an integrated circuit, the device comprising:

a semiconductor substrate;

a voltage discharge region overlying an inner portion of the semiconductor substrate, the voltage discharged region comprising;

a plurality of conductive regions arranged as an array, the array being numbered from 1 through N in a first direction and the array being numbered from 1 through M in a second direction;

a dielectric material provided spatially around each of the conductive regions to form a thickness of material having a surface region;

an input region coupled to a first region of the plurality of conductive regions;

an output region coupled to a second region of the plurality of conductive regions;

an input line provided overlying a first region of the semiconductor substrate region and coupled to the input region of the plurality of conductive regions; and

an output line provided overlying a second region of the semiconductor substrate region and coupled to the output region of the plurality of conductive regions.

2. The device of claim 1 wherein the input line is coupled to a bond pad.

3. The device of claim 1 wherein the input line is coupled to an input pad.

4. The device of claim 1 wherein the input line is coupled to one or more integrated circuit modules.

5. The device of claim 1 wherein the output line is coupled to a ground potential.

6. The device of claim 1 wherein the output line is coupled to one or more integrated circuit modules.

7. The device of claim 1 wherein the plurality of conductive regions comprise, respectively, a plurality of pillars.

8. The device of claim 1 wherein each of the plurality of conductive regions is characterized by a column shape.

9. The device of claim 1 wherein each pair of the conductive regions is separated by a portion of the dielectric material.

10. The device of claim 9 wherein the dielectric material is selected from air, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric species.

11. The device of claim 1 wherein at least two of the conductive regions is separated by a predetermined gap, the gap including a portion of dielectric material therein provided a breakdown voltage between the two conductive regions.

12. The device of claim 1 wherein the array is configured in a regular pattern.

13. The device of claim 1 wherein the array is configured in an irregular pattern.

14. The device of claim 1 wherein one or more of the conductive regions comprises a regular shape and one or more of the conductive regions comprises an irregular shape.

15. The device of claim 1 wherein the voltage discharge region comprises an overlying dielectric layer and the plurality of conductive regions are formed overlying the dielectric layer.

16. The device of claim 1 wherein the plurality of conductive regions are provided by a micromachining process.

17. The device of claim 1 wherein the first direction and the second direction are parallel to the semiconductor substrate.

18. The device of claim 1 wherein the first direction and the second direction are normal to the semiconductor substrate.