Multiple chips bonded to packaging structure with low noise and multiple selectable functions

• US 8,148,806 B2
• Filed: 11/12/2008
• Issued: 04/03/2012
• Est. Priority Date: 05/19/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Peng, Bryan
• Primary Examiner(s): Williams, A O
• Application Number:
  US12/269,053
• Publication Number:
  US 20090057919A1
• Time in Patent Office: 1,238 Days
• Field of Search: 257/686, 257/E25.013, 257/E25.011, 257/E25.03, 257/685, 257/E23.079, 257/777, 257/784, 257/723, 257/738, 257/778, 257/202, 257/204, 257/208, 257/210, 257/280, 257/724, 257/528, 257/532, 257/781, 257/779, 257/786, 257/E23.004, 257/E23.067, 257/E23.069, 257/675, 257/737, 257/773, 257/691, 257/698
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/141 : One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 2201/09309 : Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10674 : Flip chip

Abstract

The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first chip and the second chip. The second bumps connect the first chip and the second region of the substrate, wherein the second chip is over the first region of the substrate. The second bumps have a height greater than that of the first bumps plus the second chip. The substrate does not have an opening accommodating the second chip. The first bumps may be gold bumps or solder bumps. The second bumps may be solder bumps.

Claims

1. A chip package comprising:

a first circuit substrate comprising a first pad at a top side of said first circuit substrate;

a first solder ball contacting a bottom side of said first circuit substrate;

a first chip over said top side of said first circuit substrate, wherein said first chip is connected to said first pad;

a second chip over said first chip; and

a portion over said top side of said first circuit substrate and over said first and second chips, wherein said portion comprises a second circuit substrate over said top side of said first circuit substrate and over said first and second chips, a third chip over a top side of said second circuit substrate, a second solder ball having a top end contacting a bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate, and a third solder ball having a top end contacting said bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate, wherein said second circuit substrate comprises a second pad at said top side of said second circuit substrate, wherein said third chip is connected to said second pad, wherein said first and second chips are directly horizontally between said second and third solder balls, wherein said first and second chips are between said top side of said first circuit substrate and said bottom side of said second circuit substrate.

2. The chip package of claim 1 further comprising a metal bump between said first chip and said top side of said first circuit substrate.

3. The chip package of claim 1 further comprising a solder bump between said first chip and said top side of said first circuit substrate.

4. The chip package of claim 1, wherein said portion further comprises a metal bump between said third chip and said top side of said second circuit substrate.

5. The chip package of claim 1, wherein said portion further comprises a solder bump between said third chip and said top side of said second circuit substrate.

6. The chip package of claim 1, wherein said portion further comprises a capacitor on said second circuit substrate.

7. The chip package of claim 1 further comprising a metal bump between said second chip and said bottom side of said second circuit substrate.

27. The chip package of claim 1, wherein said first solder ball has a height greater than a vertical distance between a top side of said first chip and a bottom side of said second chip.

28. The chip package of claim 1, wherein said second solder ball has a height greater than a vertical distance between a top side of said first chip and a bottom side of said second chip.

8. A chip package comprising:

a first circuit substrate comprising a first pad at a top side of said first circuit substrate;

a first solder ball contacting a bottom side of said first circuit substrate;

a first chip over said top side of said first circuit substrate, wherein said first chip is connected to said first pad;

a second chip over said first chip;

a second circuit substrate over said top side of said first circuit substrate and over said first and second chips, wherein said second circuit substrate comprises a second pad at a top side of said second circuit substrate, wherein said first and second chips are between said top side of said first circuit substrate and a bottom side of said second circuit substrate;

a second solder ball having a top end contacting said bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate;

a third solder ball having a top end contacting said bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate, wherein said first and second chips are directly horizontally between said second and third solder balls;

a third chip over said top side of said second circuit substrate, wherein said third chip is connected to said second pad; and

a fourth chip over said third chip.

9. The chip package of claim 8 further comprising a metal bump between said first chip and said top side of said first circuit substrate.

10. The chip package of claim 8 further comprising a solder bump between said first chip and said top side of said first circuit substrate.

11. The chip package of claim 8 further comprising a metal bump between said third chip and said top side of said second circuit substrate.

12. The chip package of claim 8 further comprising a solder bump between said third chip and said top side of said second circuit substrate.

13. The chip package of claim 8 further comprising a third circuit substrate over said top side of said second circuit substrate and over said third and fourth chips, a fourth solder ball having a top end on a bottom side of said third circuit substrate and a bottom end on said top side of said second circuit substrate, and a fifth solder ball having a top end on said bottom side of said third circuit substrate and a bottom end on said top side of said second circuit substrate, wherein said third and fourth chips are directly horizontally between said fourth and fifth solder balls.

14. The chip package of claim 8 further comprising a metal bump between said second chip and said bottom side of said second circuit substrate.

25. The chip package of claim 8, wherein said second circuit substrate has a thickness greater than a vertical distance between a top side of said third chip and a bottom side of said fourth chip.

29. The chip package of claim 8, wherein said first solder ball has a height greater than a vertical distance between a top side of said first chip and a bottom side of said second chip.

30. The chip package of claim 8, wherein said first solder ball has a height greater than a vertical distance between a top side of said third chip and a bottom side of said fourth chip.

31. The chip package of claim 8, wherein said second solder ball has a height greater than a vertical distance between a top side of said first chip and a bottom side of said second chip.

32. The chip package of claim 8, wherein said second solder ball has a height greater than a vertical distance between a top side of said third chip and a bottom side of said fourth chip.

15. A chip package comprising:

a portion comprising a first circuit substrate, a first solder ball contacting a bottom side of said first circuit substrate, and a first chip over a top side of said first circuit substrate, wherein said first chip is connected to a first pad of said first circuit substrate at said top side of said first circuit substrate;

a second circuit substrate over said top side of said first circuit substrate and over said first chip, wherein said second circuit substrate comprises a second pad at a top side of said second circuit substrate, wherein said first chip is between said top side of said first circuit substrate and a bottom side of said second circuit substrate;

a second solder ball having a top end contacting said bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate;

a third solder ball having a top end contacting said bottom side of said second circuit substrate and a bottom end contacting said top side of said first circuit substrate, wherein said first chip is directly horizontally between said second and third solder balls;

a second chip over said top side of said second circuit substrate, wherein said second chip is connected to said second pad; and

a third chip over said second chip wherein said second solder ball has a height greater than a vertical distance between a top side of said second chip and a bottom side of said third chip.

16. The chip package of claim 15, wherein said portion further comprises a metal bump between said first chip and said top side of said first circuit substrate.

17. The chip package of claim 15, wherein said portion further comprises a solder bump between said first chip and said top side of said first circuit substrate.

18. The chip package of claim 15 further comprising a metal bump between said second chip and said top side of said second circuit substrate.

19. The chip package of claim 15 further comprising a solder bump between said second chip and said top side of said second circuit substrate.

20. The chip package of claim 15 further comprising a third circuit substrate over said top side of said second circuit substrate and over said second and third chips, a fourth solder ball having a top end on a bottom side of said third circuit substrate and a bottom end on said top side of said second circuit substrate, and a fifth solder ball having a top end on said bottom side of said third circuit substrate and a bottom end on said top side of said second circuit substrate, wherein said second and third chips are directly horizontally between said fourth and fifth solder balls.

26. The chip package of claim 15, wherein said second circuit substrate has a thickness greater than a vertical distance between a top side of said second chip and a bottom side of said third chip.

21. A chip package comprising:

a circuit substrate;

a first metal bump contacting a bottom side of said circuit substrate;

a first chip over a top side of said circuit substrate;

a second metal bump between a top side of said circuit substrate and a bottom side of said first chip, wherein said second metal bump has a top end contacting said bottom side of said first chip and a bottom end contacting said top side of said circuit substrate;

a second chip over said first chip and said top side of said circuit substrate;

a third chip over said second chip and said top side of said circuit substrate;

a third metal bump between a top side of said second chip and a bottom side of said third chip, wherein said third metal bump has a bottom end contacting said top side of said chip;

a fourth chip over said third chip and said top side of said circuit substrate; and

a fourth metal bump between a top side of said third chip and said fourth chip, wherein said fourth metal bump has a bottom end contacting said top side of said third chip, wherein said first metal bump has a height greater than that of said second metal bump, than that of said third metal bump, than that of said fourth metal bump and than a vertical distance between a top side of said first chip and a bottom side of said second chip.

22. The chip package of claim 21, wherein said second metal bump comprises a gold bump.

23. The chip package of claim 21, wherein said second metal bump comprises a solder bump.

24. The chip package of claim 21 further comprising a fifth chip under said bottom side of said circuit substrate, and a fifth metal bump having a bottom end contacting a top side of said fifth chip and a top end contacting said bottom side of said circuit substrate.

33. The chip package of claim 21, wherein said third metal bump comprises a gold bump.

34. The chip package of claim 21, wherein said third metal bump comprises a solder bump.