Reference current generating circuit

• US 8,148,970 B2
• Filed: 03/08/2010
• Issued: 04/03/2012
• Est. Priority Date: 09/02/2009
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fuse, Tsuneaki, Ichikawa, Masaki
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US12/719,320
• Publication Number:
  US 20110050196A1
• Time in Patent Office: 757 Days
• Field of Search: 323311-314, 327/539, 327/543
• US Class Current: 323/313
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A reference current generating circuit includes first and second standard current generating circuits to generate first and second standard currents, respectively and first and second trimming circuits to generate first and second reference circuits by trimming the standard current values outputted from the standard current generating circuits. The second standard current generating circuit operates for a part of an operation period of the first standard current generating circuit. The value of the first reference current is compared with a value of the second reference current, and controlled so as to approach the value of the second reference current by a trimming controller.

Claims

1. A reference current generating circuit comprising:

a first standard current generating circuit to generate a first standard current;

a second standard current generating circuit to generate a second standard current by operating for a part of an operation period of the first standard current generating circuit;

a first trimming circuit to generate a first reference current by trimming the value of the first standard current;

a second trimming circuit to generate a second reference current by trimming the value of the second standard current;

a comparison circuit to compare a value of the first reference current with a value of the second reference current; and

a trimming controller to control the trimming of the first trimming circuit so that the value of the first reference current approaches the value of the second reference current.

2. The reference current generating circuit according to claim 1, wherein each of the first and second trimming circuits includes;

M first field effect transistors (M is an integer not less than

     2) conducting mirror operation based on the first standard current, and

a switch to select the first field effect transistors to generate the first and second reference currents by merging current through the selected first field effect transistors, respectively.

3. The reference current generating circuit according to claim 2, wherein each of the first and second standard current generating circuits includes;

an operational amplifier to receive a reference voltage at one input terminal,

a second field effect transistor having a gate and drain, an output of the operational amplifier being applied to the gate, and

k resistors (k is an integer not less than

     2) connected in series to the drain of the second field effect transistor and feed backing a voltage at one of connection points of the resistors to the other input terminal of the operational amplifier.

4. The reference current generating circuit according to claim 3, wherein each of the first and second standard current generating circuits includes a capacitor connected to the gate of the second field effect transistor.

5. The reference current generating circuit according to claim 3, wherein the size and shape of the first field effect transistor are the same as those of the second field effect transistor.

6. The reference current generating circuit according to claim 1, further including a first resister to store the trimming value of the first trimming circuit and a second resister to store the trimming value of the second trimming circuit.

7. The reference current generating circuit according to claim 6, wherein the first and second resisters are formed of a volatile memory and a non-volatile memory, respectively.

8. The reference current generating circuit according to claim 7, wherein the volatile memory is DRAM or SRAM, and the non-volatile memory is a flash memory, respectively.

9. The reference current generating circuit according to claim 1, further including a power supply controller to supply a power to the second standard current generating circuit when the power is on, and shuts the power supply to the second standard current generating circuit after the trimming control by the trimming circuit has finished.

10. The reference current generating circuit according to claim 1, wherein the comparison circuit includes an operational amplifier and an A/D converter to convert the output of the operational amplifier to digital signal, and the A/D converter is connected to the trimming controller.

11. The reference current generating circuit according to claim 10, wherein the comparison circuit includes a third field effect transistor having a drain and a gate to receive the output of the operational amplifier, and at least two resistors connected to the drain in series, and either one of connection points of the resistors is connected to an input terminal of the A/D converter.

12. The reference current generating circuit according to claim 11, further including first and second current/voltage conversion circuits to convert the first and second reference currents to voltages, respectively, and the outputs of the first and second current/voltage conversion circuits are applied to the operational amplifier in the comparison circuit.

13. The reference current generating circuit according to claim 1, further including a sense circuit connected to the first trimming circuit to determine the read data from a memory cell by comparing the first reference current and the cell current, when the cell current is greater than the first reference current, the read data is “

1”

, and when the cell current is smaller than the first reference current, the read data is “

0”

.

14. The reference current generating circuit according to claim 13, wherein the sense circuit includes a sense amplifier switched between a voltage sense or a current sense by a sense enable signal.

15. A reference current generating circuit comprising:

a first standard current generating circuit to generate a first standard current;

a second standard current generating circuit to generate a second standard current by operating for a part of an operation period of the first standard current generating circuit;

a first trimming circuit to generate a first reference current by trimming the value of the first standard current;

a second trimming circuit to generate a second reference current by trimming the value of the second standard current;

a comparison circuit to compare the value of the first reference current with the value of the second reference current;

a trimming controller to control the trimming of the first trimming circuit so that the value of the first reference current approaches the value of the second reference current;

a sense circuit to compare the first reference current with a cell current read from a memory cell;

an error correction circuit to correct error data read from the memory cell;

an error frequency determiner to determine the error frequency based on the corrected result by the error correction circuit; and

a power supply controller to control power supply to the second standard current generating circuit based on the decision by the error frequency determiner.

16. The reference current generating circuit according to claim 15, wherein each of the first and second trimming circuits includes;

M field effect transistors (M is an integer not less than

     2) conducting mirror operation based on the first standard current, and

a switch to select the field effect transistors to generate the first and second reference currents by merging current through the selected field effect transistors, respectively.

17. The reference current generating circuit according to claim 15, further comprising a first resister to store the trimming value of the first trimming circuit and a second resister to store the trimming value of the second trimming circuit.

18. The reference current generating circuit according to claim 15, wherein if the error frequency determined by the error frequency determiner is not more than a predetermined value, the power supply to the second standard current generating circuit is stopped by the power supply controller to maintain a state in which the second reference current is not generated.

19. The reference current generating circuit according to claim 15, wherein if the error frequency determined by the error frequency determiner exceeds the predetermined value, the power supply to the second standard current generating circuit is performed by the power supply controller, and the second reference current trimmed in a second trimming circuit is generated.