Delay lines, methods for delaying a signal, and delay lock loops

• US 8,149,034 B2
• Filed: 01/07/2011
• Issued: 04/03/2012
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gomm, Tyler
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Houston, Adam
• Application Number:
  US12/986,973
• Publication Number:
  US 20110102029A1
• Time in Patent Office: 452 Days
• Field of Search: 327/149, 327/158
• US Class Current: 327/158
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.

Claims

1. A method of delaying a reference clock signal, comprising:

generating a plurality of delayed signals each of which is delayed relative to another one of the delayed signals by a coarse delay interval, the delayed signals having delays differing from each other by one coarse delay interval being inverted from each other;

selecting one of the delayed signals and applying the selected delayed signal to a first output;

inverting another one of the delayed signals having a delay differing from the delay of the selected delayed signal by a single coarse delay interval; and

applying the inverted delayed signal to a second output.

2. The method of claim 1 wherein the selected delayed signal is applied to the first output with a propagation delay that is substantially equal to a propagation delay at which the other one of the delayed signals is applied to the second output.

3. The method of claim 1 wherein the delayed signals are generated by respective series coupled inverting delay devices, and wherein the method further comprises disabling inverting delay devices downstream from the inverting delay device generating the selected delayed signal.

7. The method of claim 1, further comprising:

phase mixing the signals applied to the first and second outputs to provide an output clock signal.

8. The method of claim 7 wherein phase mixing the signals applied to the first and second outputs comprises:

interpolating between a delay between the signals applied to the first and second outputs.

9. The method of claim 1 wherein applying the selected delayed signal to a first output comprises inverting the selected delayed signal twice before applying the selected delayed signal, and wherein inverting another one of the delayed signals comprises inverting the selected delayed signal three times.

10. The method of claim 9 wherein a propagation delay for inverting the selected delayed signal once is longer than a propagation delay for inverting the another one of the delayed signal once.

11. The method of claim 9, further comprising balancing loads for inverting the selected delayed signal twice and the inverting the another one of the delayed signals.

12. The method of claim 1 wherein one coarse delay interval is equal to a propagation delay of a single inverting delay device.

14. The method of claim 12 wherein sequentially inverting and delaying the reference clock signal comprises:

providing the reference clock signal to a delay line having a plurality of delay stages, wherein each delay stage has a single inverting delay device.

15. The method of claim 14 wherein the single inverting delay device comprises a NAND gate.

4. A method of synchronizing an output clock signal to a reference clock signal, comprising:

sequentially inverting and delaying the reference clock signal by a sequence of coarse delays so that a plurality of delayed signals are generated each of which is inverted and delayed from a prior delayed signal by one coarse delay;

selecting two of the delayed signals, the selected delayed signals having respective delays that differ from each other by one coarse delay;

inverting one of the selected delayed signals without inverting the other of the selected signals;

using the selected delayed signals and an interpolation value to interpolate between the delay of the inverted delayed signal and the delay of the other one of the delayed signal to provide an output clock signal; and

comparing the timing of the reference clock signal to the timing of the output clock signal to determine the selected delayed signals and the interpolation value.

5. The method of claim 4 wherein the delay of the inverted delayed signal differs from the delay of the other of the delayed signals by substantially one coarse delay.

6. The method of claim 4 wherein the delayed signals are generated by respective series coupled inverting delay devices, and wherein the method further comprises disabling inverting delay devices downstream from the inverting delay device generating the selected delayed signal.

13. The method of claim 4 wherein comparing the timing of the reference clock signal to the timing of the output signal comprises:

delaying the output signal by a model delay to provide a feedback signal; and

determining a phase difference between the reference clock signal and the feedback signal,

wherein the selected delayed signals and the interpolation value are determined based at least in part on the phase difference.

16. The method of claim 4 wherein inverting one of the selected delayed signals without inverting the other of the selected signals comprises propagating the one of the selected delayed signals through an odd number of inverters and propagating the other of the selected signals through an even number of inverters, at least one of the even number of inverters has different electrical characteristics from at least one of the odd number of inverters.

17. The method of claim 16 wherein a propagation delay for at least one of the even number of inverters is shorter than a propagation delay for at least one of the odd number of inverters.

18. The method of claim 4 wherein inverting one of the selected delayed signals without inverting the other of the selected signals comprises propagating the one of the selected delayed signals through an inverting delay and propagating the other of the selected signals through a non-inverting delay, the propagation delay for the inverting and non-inverting delays are substantially equal.

19. The method of claim 4 wherein using the selected delayed signals and an interpolation value to interpolate between the delay of the inverted delayed signal and the delay of the other one of the delayed signal adds a fine delay to provide the output clock signal.

20. The method of claim 4 wherein one of the two selected delayed signals is provided by inverting the other one of the two selected delayed signals.