Techniques for phase adjustment

• US 8,149,038 B1
• Filed: 03/22/2010
• Issued: 04/03/2012
• Est. Priority Date: 03/22/2010
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Sung, Chiakang, Bui, John Henry, Nguyen, Khai, Wang, Bonnie I., Wang, Xiaobao
• Primary Examiner(s): LUU, AN T
• Application Number:
  US12/729,114
• Time in Patent Office: 743 Days
• Field of Search: 327/7, 327/12, 327 41- 42, 327/156, 327158-161
• US Class Current: 327/231
• CPC Class Codes: H03K 2005/00293 Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled

Abstract

A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

Claims

1. A dynamic phase alignment circuit comprising:

a phase generator circuit comprising delay-locked loop circuits operable to generate periodic output signals, wherein each of the delay-locked loop circuits is operable to generate one of the periodic output signals in response to at least two periodic input signals;

a multiplexer circuit operable to provide a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals;

a phase detection circuit operable to compare a phase of the selected periodic signal to a data signal to generate a phase detection signal; and

a first control logic circuit operable to generate the select signals, wherein the first control logic circuit is operable to adjust the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal,

wherein each of the delay-locked loop circuits comprises a shift register operable to cause a delay provided to a first delayed signal to vary based on a phase comparison between the first delayed signal and a first one of the periodic input signals, and wherein a second one of the periodic input signals is delayed to generate the first delayed signal.

2. The dynamic phase alignment circuit of claim 1 wherein each of the delay-locked loop circuits further comprises:

a phase comparator circuit operable to generate a phase comparison signal based on the first one of the periodic input signals and the first delayed signal,

wherein the shift register is operable to generate delay control signals, and wherein the shift register is clocked by the phase comparison signal; and

a delay chain comprising adjustable delay circuits, wherein the delay control signals control delays of the adjustable delay circuits, and wherein the delay chain is operable to generate the first delayed signal.

3. The dynamic phase alignment circuit of claim 2 wherein the phase comparator circuit in each of the delay-locked loop circuits comprises:

a first flip-flop comprising a first input operable to receive the first one of the periodic input signals and a second input operable to receive the first delayed signal;

a second flip-flop comprising a first input operable to receive the first one of the periodic input signals and a second input operable to receive an output signal of the first flip-flop; and

a first logic gate circuit comprising a first input operable to receive the output signal of the first flip-flop and a second input operable to receive the first one of the periodic input signals.

4. The dynamic phase alignment circuit of claim 3 wherein the phase comparator circuit in each of the delay-locked loop circuits further comprises:

a third flip-flop comprising a first input operable to receive the first one of the periodic input signals and a second input operable to receive an output signal of the second flip-flop, and wherein the first logic gate circuit comprises a third input operable to receive an output signal of the third flip-flop.

5. The dynamic phase alignment circuit of claim 4 wherein each of the delay-locked loop circuits further comprises:

a fourth flip-flop comprising a first input operable to receive a second delayed signal generated by the delay chain and a second input operable to receive the first one of the periodic input signals, wherein the delay chain is operable to receive the second one of the periodic input signals; and

a fifth flip-flop comprising a first input operable to receive an output signal of the fourth flip-flop and a second input operable to receive the output signal of the first flip-flop, wherein the fifth flip-flop is operable to store a signal that controls the delays of the adjustable delay circuits.

6. The dynamic phase alignment circuit of claim 5 wherein each of the delay-locked loop circuits further comprises a second logic gate circuit comprising a first input operable to receive the signal stored by the fifth flip-flop and a second input operable to receive an input signal, and wherein the second logic gate circuit is operable to cause the shift register to drive one of the delay control signals to a predefined logic state in response to a change in an output signal of the second logic gate circuit.

7. The dynamic phase alignment circuit of claim 4 wherein each of the delay-locked loop circuits further comprises:

a fourth flip-flop comprising a first input operable to receive a second delayed signal generated by the delay chain and a second input operable to receive the first one of the periodic input signals; and

a second control logic circuit operable to cause the shift register to drive at least a subset of the delay control signals to predefined logic states in response to an output signal of the fourth flip-flop and the output signal of the first flip-flop.

8. The dynamic phase alignment circuit of claim 2 wherein each of the adjustable delay circuits in the delay chain comprises a first pass gate coupled between a first capacitor and an output node of the adjustable delay circuit and a second pass gate coupled between a second capacitor and the output node of the adjustable delay circuit.

9. The dynamic phase alignment circuit of claim 1 wherein the dynamic phase alignment circuit is in a field programmable gate array integrated circuit, and wherein the phase detection circuit comprises phase detector circuits and counter circuits.

10. The dynamic phase alignment circuit of claim 1 wherein the phase generator circuit comprises at least 8 delay-locked loop circuits that generate 8 periodic output signals.

11. A circuit comprising:

a phase comparator circuit operable to generate a phase comparison signal in response to a first delayed signal and a first periodic input signal;

a shift register comprising storage circuits operable to generate delay control signals, wherein the storage circuits are operable to update the delay control signals in response to the phase comparison signal; and

a delay chain comprising adjustable delay circuits, wherein delays of the adjustable delay circuits are operable to vary based on changes in the delay control signals, and wherein the delay chain is operable to delay a second periodic input signal to generate the first delayed signal,

wherein each of the adjustable delay circuits in the delay chain comprises a first pass gate coupled between a first capacitor and an output node of the adjustable delay circuit and a second pass gate coupled between a second capacitor and the output node of the adjustable delay circuit, and wherein the first and the second pass gates are controlled by the delay control signals.

12. The circuit of claim 11 wherein a high supply voltage is transmitted to an input of a first one of the storage circuits, and wherein logic high signals are shifted through the storage circuits in response to edges of the phase comparison signal.

13. The circuit of claim 11 wherein a ground voltage is transmitted to an input of a first one of the storage circuits, and wherein logic low signals are shifted through the storage circuits in response to edges of the phase comparison signal.

14. The circuit of claim 11 wherein the phase comparator circuit comprises:

a first flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive the first delayed signal; and

a second flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive an output signal of the first flip-flop.

15. The circuit of claim 11 wherein each of the adjustable delay circuits in the delay chain comprises a third capacitor coupled to the first capacitor and a fourth capacitor coupled to the second capacitor.

16. A circuit comprising:

a phase comparator circuit operable to generate a phase comparison signal in response to a first delayed signal and a first periodic input signal;

a shift register comprising storage circuits operable to generate delay control signals, wherein the storage circuits are operable to update the delay control signals in response to the phase comparison signal; and

a delay chain comprising adjustable delay circuits, wherein delays of the adjustable delay circuits are operable to vary based on changes in the delay control signals, and wherein the delay chain is operable to delay a second periodic input signal to generate the first delayed signal,

wherein the phase comparator circuit comprises;

a first flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive the first delayed signal;

a second flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive an output signal of the first flip-flop;

a third flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive an output signal of the second flip-flop; and

a first logic gate circuit comprising a first input operable to receive the output signal of the first flip-flop, a second input operable to receive the first periodic input signal, and a third input operable to receive an output signal of the third flip-flop.

17. The circuit of claim 16 further comprising:

a fourth flip-flop comprising a first input operable to receive a second delayed signal generated by the delay chain and a second input operable to receive the first periodic input signal; and

a fifth flip-flop comprising a first input operable to receive an output signal of the fourth flip-flop and a second input operable to receive the output signal of the first flip-flop, wherein the fifth flip-flop stores a signal that controls the delays of the adjustable delay circuits.

18. The circuit of claim 17 further comprising:

a second logic gate circuit comprising a first input operable to receive the signal stored by the fifth flip-flop and a second input operable to receive an input signal, wherein the second logic gate circuit is operable to cause the shift register to drive one of the delay control signals to a predefined logic state in response to a change in an output signal of the second logic gate circuit.

19. The circuit of claim 16 further comprising:

a fourth flip-flop comprising a first input operable to receive a second delayed signal generated by the delay chain and a second input operable to receive the first periodic input signal; and

a control logic circuit operable to cause the shift register to drive at least a subset of the delay control signals to predefined logic states in response to an output signal of the fourth flip-flop and the output signal of the first flip-flop.

20. A circuit comprising:

a phase comparator circuit operable to generate a phase comparison signal in response to a first delayed signal and a first periodic input signal;

a shift register comprising storage circuits operable to generate delay control signals, wherein the storage circuits are operable to update the delay control signals in response to the phase comparison signal; and

a delay chain comprising adjustable delay circuits, wherein delays of the adjustable delay circuits are operable to vary based on changes in the delay control signals, and wherein the delay chain is operable to delay a second periodic input signal to generate the first delayed signal,

wherein the phase comparator circuit comprises;

a first flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive the first delayed signal; and

a second flip-flop comprising a first input operable to receive the first periodic input signal and a second input operable to receive a second delayed signal, wherein the first delayed signal is inverted to generate the second delayed signal,

wherein the shift register comprises a first input that is responsive to an output signal of the first flip-flop and a second input that is responsive to an output signal of the second flip-flop.

21. A method comprising:

generating periodic output signals in response to periodic input signals using delay-locked loops, wherein each of the delay-locked loops generates one of the periodic output signals based on at least two of the periodic input signals, and wherein each of the delay-locked loops comprises a shift register that causes a delay provided to a first delayed signal to vary based on a phase comparison between the first delayed signal and a first one of the periodic input signals, and wherein a second one of the periodic input signals is delayed to generate the first delayed signal;

selecting a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals;

comparing a phase of the selected periodic signal to a data signal to generate a phase detection signal; and

generating the select signals and adjusting the select signals based on changes in the phase detection signal in order to cause an adjustment in the phase of the selected periodic signal.

22. The method of claim 21 wherein generating periodic output signals in response to periodic input signals using delay-locked loops further comprises:

comparing phases of the first delayed signal and the first one of the periodic input signals to generate a phase comparison signal;

generating delay control signals by shifting signals through the shift register, wherein the shift register is driven by the phase comparison signal;

adjusting delays of delay circuits coupled in a delay chain based on the delay control signals; and

generating the first delayed signal in response to the second one of the periodic input signals using the delay chain.

23. The method of claim 22 wherein comparing phases of the first delayed signal and the first one of the periodic input signals to generate a phase comparison signal further comprises:

storing a first stored signal in response to the first delayed signal and the first one of the periodic input signals;

storing a second stored signal in response to the first stored signal and the first one of the periodic input signals; and

generating the phase comparison signal by performing a logic function on the first stored signal and the first one of the periodic input signals.

24. The method of claim 23 wherein comparing phases of the first delayed signal and the first one of the periodic input signals to generate a phase comparison signal further comprises:

storing a third stored signal in response to the second stored signal and the first one of the periodic input signals, and

wherein generating the phase comparison signal by performing a logic function on the first stored signal and the first one of the periodic input signals further comprises generating the phase comparison signal by performing the logic function on the first stored signal, the first one of the periodic input signals, and the third stored signal.

25. The method of claim 24 wherein generating periodic output signals in response to periodic input signals using delay-locked loops further comprises:

storing a fourth stored signal in response to the first one of the periodic input signals and a second delayed signal generated by the delay chain; and

storing a fifth stored signal in response to the fourth stored signal and the first stored signal, wherein the fifth stored signal controls the delays of the delay circuits.

26. The method of claim 25 wherein generating periodic output signals in response to periodic input signals using delay-locked loops further comprises:

generating a control signal that causes the shift register to drive one of the delay control signals to a predefined logic state by performing a logic function on the fifth stored signal and an input signal.

27. The method of claim 24 wherein generating periodic output signals in response to periodic input signals using delay-locked loops further comprises:

storing a fourth stored signal in response to the first one of the periodic input signals and a second delayed signal generated by the delay chain; and

generating register control signals that cause the shift register to drive at least a subset of the delay control signals to predefined logic states in response to the fourth stored signal and the first stored signal.

28. The method of claim 22 wherein generating the first delayed signal in response to the second one of the periodic input signals using the delay chain further comprises inverting the second one of the periodic input signals using first and second transistors, and wherein adjusting delays of delay circuits coupled in a delay chain based on the delay control signals further comprises:

increasing a delay provided to the first delayed signal based on the delay control signals by coupling first and second capacitors to an output node of one of the delay circuits, wherein the first and the second capacitors are coupled between a first node at a high voltage and a second node at a low voltage; and

increasing the delay provided to the first delayed signal based on the delay control signals by coupling third and fourth capacitors to the output node, wherein the third and the fourth capacitors are coupled between the first and the second nodes.

29. A method comprising:

comparing phases of a first delayed signal and a first periodic input signal to generate a phase comparison signal;

generating delay control signals by shifting signals through a shift register;

updating the delay control signals based on the phase comparison signal;

adjusting delays of delay circuits coupled in a delay chain based on the delay control signals; and

generating the first delayed signal in response to a second periodic input signal using the delay chain,

wherein comparing phases of a first delayed signal and a first periodic input signal to generate a phase comparison signal comprises;

storing a first stored signal in response to the first delayed signal and the first periodic input signal;

storing a second stored signal in response to the first stored signal and the first periodic input signal;

storing a third stored signal in response to the second stored signal and the first periodic input signal; and

generating the phase comparison signal by performing a logic function on the first stored signal, the first periodic input signal, and the third stored signal.

30. The method of claim 29 further comprising:

storing a fourth stored signal in response to the first periodic input signal and a second delayed signal generated by the delay chain; and

storing a fifth stored signal in response to the fourth stored signal and the first stored signal, wherein the fifth stored signal controls the delays of the delay circuits.

31. The method of claim 30 further comprising:

generating a control signal that causes the shift register to drive one of the delay control signals to a predefined logic state by performing a logic function on the fifth stored signal and an input signal.

32. The method of claim 29 further comprising:

storing a fourth stored signal in response to the first periodic input signal and a second delayed signal generated by the delay chain; and

generating register control signals that cause the shift register to drive at least a subset of the delay control signals to predefined logic states in response to the fourth stored signal and the first stored signal.

33. The method of claim 29 wherein each of at least a subset of the delay circuits in the delay chain comprises a first pass gate coupled between a first capacitor and an output node of the delay circuit and a second pass gate coupled between a second capacitor and the output node of the delay circuit, and wherein the first and the second pass gates are controlled by the delay control signals.