Flash memory device having dummy cell

• US 8,149,620 B2
• Filed: 03/02/2009
• Issued: 04/03/2012
• Est. Priority Date: 01/09/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Sang-gu
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US12/395,730
• Publication Number:
  US 20090168526A1
• Time in Patent Office: 1,128 Days
• Field of Search: 365/185.11, 365/185.17, 365/185.2, 365/185.23
• US Class Current: 365/185.11
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a cell array including a plurality of blocks each of which is formed of a plurality of strings, each string including a plurality of memory cells assigned by an external address and connected to corresponding word lines and at least one memory cell not assigned by the external address and connected to a dummy word line;

a storage device configured to store position data that selects the at least one memory cell;

a pre-decoder configured to translate the external address to an internal address in response to the position data;

a decoder configured to supply word line voltages to the word lines in response to the internal address and a control signal;

a control unit configured to generate the control signal in response to the position data,

wherein the control unit controls a driver so that the at least one memory cell connected to the dummy word line is programmed to a predetermined state after an erase operation.

2. The nonvolatile semiconductor memory device as set forth in claim 1, wherein the internal address comprises information which selects the dummy word line.

3. The nonvolatile semiconductor memory device as set forth in claim 1, wherein a position of the dummy word line is determined to minimize a charge sharing in a string including a program-inhibited memory cell and wherein the position of the dummy word line is stored in a fuse box as the position data.

4. The nonvolatile semiconductor memory device as set forth in claim 1, wherein the position data is saved into the storage device at one of times during and after a test process.

5. The nonvolatile semiconductor memory device as set forth in claim 1, wherein the storage device comprises a fuse option block.

6. The nonvolatile semiconductor memory device as set forth in claim 1, wherein the decoder comprises a word line driver which supplies the word line voltages to the word lines and the dummy word line in response to the internal address and the control signal.

7. The nonvolatile semiconductor memory device as set forth in claim 6, wherein the word line driver applies a pass voltage to the dummy word line during a programming operation.

8. The nonvolatile semiconductor memory device as set forth in claim 6, wherein the word line driver applies a same voltage to the at least one memory cell as that applied to unselected word lines during a reading operation.

9. The nonvolatile semiconductor memory device as set forth in claim 6, wherein the word line driver applies a ground voltage to all the word lines during the erase operation.

10. The nonvolatile semiconductor memory device as set forth in claim 6, wherein the word line driver applies a program voltage to the dummy word line after the erase operation in order to program the at least one memory cell connected to the dummy word line to the predetermined state.