Electronically tuned agile integrated bandpass filter

• US 8,150,362 B2
• Filed: 03/12/2004
• Issued: 04/03/2012
• Est. Priority Date: 04/03/2003
• Status: Active Grant

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Waight, Matthew, Marsh, James, Luong, Howard
• Primary Examiner(s): TRAN, PABLO N
• Application Number:
  US10/799,900
• Publication Number:
  US 20040198298A1
• Time in Patent Office: 2,944 Days
• Field of Search: 455/333, 455/323, 455/326, 455/313, 455/332, 455286-290, 455/293, 455306-307, 455/311, 455339-341, 333/186, 333/175, 330/175, 331/100, 327/552
• US Class Current: 455/339
• CPC Class Codes: H03J 2200/08 Calibration of receivers, in particular of a band pass filter
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 5/244 using electronic means
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A method and apparatus for an electronically tuned agile integrated bandpass filter is described. In one embodiment, the invention is an intermediate frequency filter for use in an integrated circuit. The filter includes a first filter stage, including a first LC resonator. The first filter stage further includes a first adjustable capacitor array coupled to the first LC resonator. The first adjustable capacitor array has an effective capacitance value adjustable through use of a first plurality of programmable data storage locations. The first plurality of programmable data storage locations are programmable through a serial control interface.

Claims

1. An intermediate frequency filter for use in an integrated circuit, comprising:

a first filter stage, the first filter stage including a first LC resonator; and

the first filter stage further including a first adjustable capacitor array coupled to the first LC resonator, wherein the first adjustable capacitor includes one or more switched capacitor blocks, each switched capacitor block having at least one capacitor coupled in series with a switch and further coupled in series with at least one other capacitor, the first adjustable capacitor array having an effective capacitance value adjustable through use of the switch in each switched capacitor block, further wherein each switch is coupled to a switching line programmable through a serial control interface.

2. The filter of claim 1, wherein:

the first filter stage further including a second adjustable capacitor array coupled to the LC resonator, the second adjustable capacitor array having an effective capacitance value adjustable through use of a second plurality of data storage locations, the second plurality of data storage locations programmable through the serial control interface.

3. The filter of claim 2, wherein:

the data storage locations of the second plurality of data storage locations are fuses.

4. The filter of claim 1, wherein:

a first switched capacitor block including a first capacitor of a first magnitude coupled in series with a first switch and further coupled in series with a second capacitor of the first magnitude, the first switch controlled by a first switching line; and

a second switched capacitor block including a third capacitor of a second magnitude coupled in series with a second switch and further coupled in series with a fourth capacitor of the second magnitude, the second switch controlled by a second switching line, the combination of the third capacitor, second switch and fourth capacitor coupled in parallel with the combination of the first capacitor, first switch and second capacitor.

5. The filter of claim 1, wherein at least a capacitor of the LC resonator is part of the integrated circuit.

6. The filter of claim 1, wherein each switch is controlled by a programmable data storage location that is programmable through the serial control interface of the integrated circuit.

7. The filter of claim 6, wherein each programmable data storage location is programmable through a set of test points on the integrated circuit.

8. The filter of claim 1, wherein each switching line is coupled to a fuse.

9. The filter of claim 1, wherein each switch comprises a transistor.

10. The filter of claim 1, wherein each specific switched capacitor block is enabled or disabled using a control signal input to the switch via the switching line of the specific switched capacitor block, and a capacitance value of the specific switched capacitor block is set using the same control signal input to the switch.

11. A circuit formed as part of a single integrated circuit, the circuit comprising:

a first amplifier;

a first oscillator;

a first mixer coupled to the first amplifier and the first oscillator;

a second oscillator;

a second mixer coupled to the second oscillator;

a second amplifier coupled to the second mixer;

a serial control module;

an intermediate frequency filter (IF filter), the IF filter including a first filter stage, the first filter stage including a first LC resonator;

the first filter stage further including a first adjustable capacitor array coupled to the first LC resonator, wherein the first adjustable capacitor includes one or more switched capacitor blocks, each switched capacitor block having at least one capacitor coupled in series with a switch and further coupled in series with at least one other capacitor, the first adjustable capacitor array having an effective capacitance value adjustable through use of the switch in each switched capacitor block, further wherein each switch is coupled to a switching line programmable through the serial control module;

and wherein the second mixer is coupled to the IF filter and the IF filter is coupled to the first mixer.

12. The circuit of claim 11, wherein the first filter stage further includes:

a second adjustable capacitor array coupled to the LC resonator, the second adjustable capacitor array having an effective capacitance value adjustable through use of a first plurality of data storage locations, the first plurality of data storage locations programmable through the serial control interface.