Random number generation based on logic circuits with feedback
First Claim
1. A random binary sequence generator for generating a random binary sequence adapted to be used for producing random numbers, comprising:
- at least one logic circuit with a set of logic circuit inputs and a set of logic circuit outputs wherein;
said at least one logic circuit comprises a plurality of asynchronous logic inversion units connected in cascade one to another, respectively;
said plurality of asynchronous logic inversion units comprises a first and a last asynchronous logic inversion unit in the cascade, said set of logic circuit outputs comprising an output of the last asynchronous logic inversion unit and said set of logic circuit inputs comprising an input of the first asynchronous logic inversion unit, said at least one logic circuit comprising a first feedback path from the output of the last asynchronous logic inversion unit to the input of the first asynchronous logic inversion unit;
said at least one logic circuit is operated without a clock signal and autonomously by connecting said logic circuit outputs to said logic circuit inputs; and
said at least one logic circuit implements a set of Boolean functions, each of said logic circuit outputs having a value defined by a respective Boolean function of at least one of said logic circuit inputs, said respective Boolean function belonging to said set of Boolean functions;
and wherein;
said logic circuit outputs represent states of said at least one logic circuit;
said set of Boolean functions forms a state-transition function defining transitions of said states, wherein said states are arranged so as to form at least one cycle of states, said at least one cycle of states having a cycle length equal to a number of states included therein;
said at least one cycle of states has a minimum length equal to two; and
in case the cycle length is two, said at least one cycle of states is meta-stable for said at least one logic circuit operated without a clock signal and autonomously.
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Abstract
A random binary sequence generator for generating a random binary sequence adapted to be used for producing random numbers, includes at least one logic circuit corresponding to an associated finite-state machine having a state-transition function including states arranged to form cycles of states, wherein the at least one logic circuit has a set of logic circuit inputs and a set of logic circuit outputs fed back to the logic circuit inputs; the associated finite-state machine is autonomous and asynchronous; the state-transition function is void of loops; and any of the cycles of states has either a minimum length equal to three states, in case the cycle is stable, or a minimum length of two states, in case the cycle is meta-stable.
31 Citations
29 Claims
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1. A random binary sequence generator for generating a random binary sequence adapted to be used for producing random numbers, comprising:
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at least one logic circuit with a set of logic circuit inputs and a set of logic circuit outputs wherein; said at least one logic circuit comprises a plurality of asynchronous logic inversion units connected in cascade one to another, respectively; said plurality of asynchronous logic inversion units comprises a first and a last asynchronous logic inversion unit in the cascade, said set of logic circuit outputs comprising an output of the last asynchronous logic inversion unit and said set of logic circuit inputs comprising an input of the first asynchronous logic inversion unit, said at least one logic circuit comprising a first feedback path from the output of the last asynchronous logic inversion unit to the input of the first asynchronous logic inversion unit; said at least one logic circuit is operated without a clock signal and autonomously by connecting said logic circuit outputs to said logic circuit inputs; and said at least one logic circuit implements a set of Boolean functions, each of said logic circuit outputs having a value defined by a respective Boolean function of at least one of said logic circuit inputs, said respective Boolean function belonging to said set of Boolean functions; and wherein; said logic circuit outputs represent states of said at least one logic circuit; said set of Boolean functions forms a state-transition function defining transitions of said states, wherein said states are arranged so as to form at least one cycle of states, said at least one cycle of states having a cycle length equal to a number of states included therein; said at least one cycle of states has a minimum length equal to two; and in case the cycle length is two, said at least one cycle of states is meta-stable for said at least one logic circuit operated without a clock signal and autonomously. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method of generating a random binary sequence adapted for producing random numbers, comprising:
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providing at least one logic circuit having a set of logic circuit inputs and a set of logic circuit outputs, wherein; said at least one logic circuit comprises a plurality of asynchronous logic inversion units connected in cascade one to another, respectively; said plurality of asynchronous logic inversion units comprises a first and a last asynchronous logic inversion unit in the cascade, said set of logic circuit outputs comprising an output of the last asynchronous logic inversion unit and said set of logic circuit inputs comprising an input of the first asynchronous logic inversion unit, said at least one logic circuit comprising a first feedback path from the output of the last asynchronous logic inversion unit to the input of the first asynchronous logic inversion unit; the at least one logic circuit implements a set of Boolean functions, each of said logic circuit outputs having a value defined by a respective Boolean function of at least one of said logic circuit inputs, said respective Boolean function belonging to said set of Boolean functions; said set of Boolean functions forms a state-transition function defining transitions of said states, wherein said states are arranged so as to form at least one cycle of states, the at least one cycle of states having a cycle length equal to a number of states included therein; and said at least one cycle of states has a minimum length equal to two; and in case the cycle length is two, said at least one cycle of states is meta-stable for said at least one logic circuit operated without a clock signal and autonomously; operating the logic circuit autonomously by feeding back the set of logic circuit outputs to said logic circuit inputs; and operating the logic circuit without a clock signal. - View Dependent Claims (25, 26, 27, 28, 29)
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Specification