Proximity-based memory allocation in a distributed memory system
First Claim
1. A system, comprising:
- a processor node comprising a processor and a network interface;
a plurality of memory nodes, wherein each memory node comprises a memory and a network interface;
a communication network configured to interconnect said processor node and said plurality of memory nodes via said network interfaces according to a network topology, wherein each of said memory nodes is removed from said processor node by a respective number of network hops according to said network topology;
wherein said processor node is configured to;
broadcast a packet comprising a memory request to a first subset of said plurality of memory nodes, wherein each memory node of said first subset of memory nodes is removed from said processor node by no more than a given number of network hops;
determine whether one or more of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request; and
in response to determining that no memory node of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request;
increase said given number of network hops; and
broadcast a packet comprising said memory request to a second subset of said plurality of memory nodes, wherein each memory node of said second subset of memory nodes is removed from said processor node by no more than said increased given number of network hops.
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Accused Products
Abstract
A system and method for allocating the nearest available physical memory in a distributed, shared memory system. In various embodiments, a processor node may broadcast a memory request to a first subset of nodes connected to it via a communication network. In some embodiments, if none of these nodes is able to satisfy the request, the processor node may broadcast the request to additional subsets of nodes. In some embodiments, each node of the first subset of nodes may be removed from the processor node by one network hop and each node of the additional subsets of nodes may be removed from the processor node by no more than an iteratively increasing number of network hops. In some embodiments, the processor node may send an acknowledgment to one node that can fulfill the request and a negative acknowledgement to other nodes that can fulfill the request.
22 Citations
20 Claims
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1. A system, comprising:
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a processor node comprising a processor and a network interface; a plurality of memory nodes, wherein each memory node comprises a memory and a network interface; a communication network configured to interconnect said processor node and said plurality of memory nodes via said network interfaces according to a network topology, wherein each of said memory nodes is removed from said processor node by a respective number of network hops according to said network topology; wherein said processor node is configured to; broadcast a packet comprising a memory request to a first subset of said plurality of memory nodes, wherein each memory node of said first subset of memory nodes is removed from said processor node by no more than a given number of network hops; determine whether one or more of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request; and in response to determining that no memory node of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request; increase said given number of network hops; and broadcast a packet comprising said memory request to a second subset of said plurality of memory nodes, wherein each memory node of said second subset of memory nodes is removed from said processor node by no more than said increased given number of network hops. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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a processor node broadcasting a packet comprising a memory request to a first subset of a plurality of memory nodes, wherein said plurality of memory nodes and said processor node are interconnected via a communication network according to a network topology, and wherein each memory node of said first subset of memory nodes is removed from said processor node by no more than a given number of network hops according to said network topology; and in response to determining that none of the memory nodes of said first subset of memory nodes has sent a reply to said processor node indicating that it can satisfy said memory request, said processor node; increasing said given number of network hops; and broadcasting a packet comprising said memory request to a second subset of said plurality of memory nodes, wherein each memory node of said second subset of memory nodes is removed from said processor node by no more than said increased given number of network hops. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A processor node, comprising:
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a processor; an input/output interface through which said processor communicates with a communication network, wherein said communication network is configured to interconnect a plurality of memory nodes according to a network topology; and execution logic configured to broadcast a packet comprising a memory request to a first subset of said plurality of memory nodes, wherein each memory node of said first subset of memory nodes is removed from said processor node by no more than a given number of network hops, and wherein the execution logic comprises one or more electronic circuits; and wherein, in response to timing out rather than receiving a reply from a memory node of said first subset of memory nodes indicating that it can satisfy said memory request, said execution logic is further configured to; increase said given number of network hops; and broadcast a packet comprising said memory request to a second subset of said plurality of memory nodes, wherein each memory node of said second subset of memory nodes is removed from said processor node by no more than said increased given number of network hops. - View Dependent Claims (19, 20)
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Specification