Controlling passthrough of communication between multiple buses

• US 8,151,029 B2
• Filed: 12/30/2010
• Issued: 04/03/2012
• Est. Priority Date: 05/21/2008
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Haban, Scott, Hester, Dylan, Sun, Ruifeng
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US12/981,769
• Publication Number:
  US 20110099310A1
• Time in Patent Office: 460 Days
• Field of Search: 710/31, 710/38, 710/52, 710/110, 710/306, 710/316, 348/725, 348/726, 348/731
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus.

Claims

1. An apparatus comprising:

a first data pad and a first clock pad to couple the apparatus to a host device via a first bus;

a second data pad and a second clock pad to couple the apparatus to a slave device via a second bus;

a first parallel input path from the first data pad to a slave controller of the apparatus and a second parallel input path from the first data pad to the second data pad, wherein the first parallel input path comprises a glitch filtered path and the second parallel input path comprises an unfiltered path; and

passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple data from the second bus to the first bus during a passthrough mode, wherein the first and second buses are electrically decoupled during the passthrough mode.

2. The apparatus of claim 1, wherein the passthrough mode between the host device and the slave device is controlled by the host device.

3. The apparatus of claim 2, wherein the host device is to write a passthrough enable indicator of a register of the apparatus to enable the passthrough mode, the passthrough mode to begin at an end of a data transaction from the host device including the passthrough enable indicator.

4. The apparatus of claim 2, wherein the host device is to enable the passthrough mode to provide information to the slave device and to disable the passthrough mode when the host device is to provide information to the apparatus.

5. The apparatus of claim 2, further comprising a slave controller to snoop passthrough communications during the passthrough mode and to control a direction of the passthrough communications through the first data pad and the second data pad based on the snooping.

6. The apparatus of claim 1, wherein the first bus is to operate at a first voltage and the second bus is to operate at a second voltage.

7. A system comprising:

a host device coupled to a first bus, the first bus coupled to a plurality of slave devices;

a first slave device coupled to the host device via the first bus and including a slave state machine of a slave controller to handle receipt and transmission of information on the first bus, a first data pad coupled to the first bus, a second data pad coupled to a second bus, a first parallel input path from the first data pad to the slave controller and a second parallel input path from the first data pad to the second data pad, wherein the first input path comprises a glitch filtered path and the second input path comprises an unfiltered path; and

a second slave device coupled to the first slave device via the second bus, wherein the second bus is to be disabled in absence of communications to or from the second slave device, and the slave state machine of the first slave device is to minor communication along the first bus to the second slave device via the second bus.

8. The system of claim 7, wherein the first slave device further comprises passthrough logic to buffer the communication along the first bus to the second bus without a direct electrical connection between the first and second buses.

9. The system of claim 7, wherein the first slave device includes:

a first parallel output path from the slave controller of the first slave device to the first data pad; and

a second parallel output path from the second data pad to the first data pad, wherein the first output path comprises a delayed path and the second output path comprises an undelayed path.

10. The system of claim 7, wherein the first slave device further comprises a first delay element clocked by a data signal of the first bus and to change state only when a clock signal of the first bus is in a high state.

11. The system of claim 10, wherein the mirrored communication is to begin when the first delay element changes state to an enable mode for the mirrored communication.

12. The system of claim 7, wherein the first bus is to operate at a first voltage and the second bus is to operate at a second voltage.

13. A method comprising:

determining whether a passthrough command has been received within a transaction from a host to a first slave device on a first bus to which a plurality of slave devices including the first slave device are coupled;

setting a passthrough mode indicator in a control register of the first slave device when the passthrough command has been received;

providing a passthrough enable signal to a passthrough circuit of the first slave device responsive to the passthrough mode indicator to enable a passthrough mode; and

buffering communications between the first bus and a second bus coupled between the first slave device and a second slave device in the passthrough mode, including providing the communications from an input pad of the first slave device to a state machine of the first slave device on a glitch filtered path, and providing the communications from the input pad to an output pad of the first slave device coupled to the second bus on an unfiltered path, the glitch filtered path and the unfiltered path comprising parallel paths from the input pad.

14. The method of claim 13, further comprising snooping data and control information communicated on the first and second buses and analyzing the data and control information in the first slave device to determine a direction of communication flow between the host and the second slave device.

15. The method of claim 14, further comprising controlling the direction of communication flow via transmission of a direction signal based on the snooping.

16. The method of claim 13, further comprising buffering the communications without electrically coupling the first and second buses, the first and second buses operating at different voltages.