Concurrent memory bank access and refresh retirement

• US 8,151,044 B2
• Filed: 12/10/2009
• Issued: 04/03/2012
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Inventors: Proesbsting, Robert
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US12/635,543
• Publication Number:
  US 20100095058A1
• Time in Patent Office: 845 Days
• Field of Search: None
• US Class Current: 711/107
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A dynamic random access memory integrated circuit and method includes internal refresh control and an array configured to receive read and write access requests having priority over pending refresh requests, wherein refresh requests are queueable and retired on clock cycles not requiring an access of the array and complete in one clock cycle. No on-board cache memory is required. A method includes: determining within the circuit when one of the banks of the array requires a refresh, prioritizing read and write access requests over pending refresh requests, read access requests initiating an access to the array without determining whether data is available from outside the array, and retiring within a clock cycle one pending refresh request to a bank when that bank has pending refresh requests and does not also require an access of the array on that clock cycle.

Claims

1. A method, comprising:

performing, by a first refresh control circuit, an access operation on a first bank of a plurality of memory banks in a memory array; and

retiring, by a second refresh control circuit and substantially simultaneously with said performing an access operation on a first bank, a pending refresh request for a second memory bank of the plurality of memory banks, wherein the pending refresh request is pending as a result of a differential comparison between a refresh request counter and a refresh address counter of the second refresh control circuit.

2. The method of claim 1, wherein said retiring occurs during a clock cycle, and wherein said performing also occurs during the clock cycle.

3. The method of claim 1, further comprising retiring, by a third refresh control circuit and substantially simultaneously with said performing an access operation on a first bank, another pending refresh request for a third memory bank of the plurality of memory banks, wherein the other pending refresh request is pending as a result of a differential comparison between a refresh request counter and a refresh address counter of the third refresh control circuit.

4. The method of claim 1, further comprising performing, by a third refresh control circuit and substantially simultaneously with said retiring a pending refresh request, another access operation on a third memory bank of the plurality of memory banks.

5. The method of claim 1, further comprising queuing, by the first refresh control circuit, another pending refresh request for the first bank of the plurality of memory banks, wherein the other pending refresh request is pending as a result of a differential comparison between a refresh request counter and a refresh address counter of the first refresh control circuit.

6. A system, comprising:

a memory array having a plurality of memory banks; and

a plurality of refresh control circuits respectively coupled to the plurality of memory banks of the memory array and configured to;

perform, by a first one of the plurality of refresh control circuits, an access operation on a first bank of the plurality of memory banks; and

retire, by a second one of the plurality of refresh control circuits and substantially simultaneously with a performance of the access operation, a pending refresh request for a second memory bank of the plurality of memory banks;

wherein the second refresh control circuit includes a refresh request counter and a refresh address counter configured to store respective counter values to enable the second refresh control circuit to use the counter values to determine whether a refresh request is pending for the second memory bank.

7. The system of claim 6, wherein the second refresh control circuit is further configured to retire the pending refresh request during a clock cycle, and wherein the first refresh control circuit is further configured to perform the access operation during the clock cycle.

8. The system of claim 6, wherein a third one of the plurality of refresh control circuits is configured to retire, substantially simultaneously with the access operation, another pending refresh request for a third memory bank of the plurality of memory banks, and wherein the third refresh control circuit includes another refresh request counter and another refresh address counter configured to store respective other counter values to enable the third refresh control circuit to use the other counter values to determine whether another refresh request is pending for the third memory bank.

9. The system of claim 6, wherein a third one of the plurality of refresh control circuits is configured to perform, substantially simultaneously with the retirement of the pending refresh request, another access operation on a third memory bank of the plurality of memory banks.

10. The system of claim 6, wherein the first refresh control circuit is further configured to determine whether a refresh request is pending for the plurality of memory banks, and wherein the first refresh control circuit includes another refresh request counter and another refresh address counter configured to store respective other counter values to enable the first refresh control circuit to use the other counter values to determine whether another refresh request is pending for the first memory bank.