Semiconductor power device with passivation layers

• US 8,153,481 B2
• Filed: 04/27/2006
• Issued: 04/10/2012
• Est. Priority Date: 04/28/2005
• Status: Active Grant

• Current Assignee: Littelfuse Incorporated
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Veeramma, Subhas Chandra Bose Jayappa
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Booker, Vicki B
• Application Number:
  US11/380,466
• Publication Number:
  US 20060246642A1
• Time in Patent Office: 2,175 Days
• Field of Search: 438/133, 438/787, 438/140, 257/E29.013
• US Class Current: 438/140
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor power device comprises a semiconductor substrate. The substrate includes an N-type silicon region and N+ silicon region. An oxide layer overlies the N− type silicon region, the oxide layer formed using a Plasma Enhanced Chemical Vapor deposition (PECVD) method. First and second electrodes are coupled to the N− type silicon region and the N+ type silicon region, respectively. The oxide layer has a thickness 0.5 to 3 microns. The power device also includes a polymide layer having a thickness of 3 to 20 microns; a first field plate overlying the oxide layer; and second field plate overlying the polymide layer and the first field plate, wherein the second field plate overlaps the first field plate by 2 to 15 microns.

Claims

1. A method of manufacturing a power semiconductor device comprising:

on a substrate of more strongly doped first conductivity type silicon, forming a less strongly first conductivity type epitaxial silicon layer;

using a plasma enhanced chemical vapor deposition process forming a first silicon dioxide layer directly on the epitaxial silicon layer;

introducing into a first region of the epitaxial layer more strongly doped first conductivity type impurity to define a channel stopper region, and introducing into a second region spaced apart from the first region an opposite conductivity type impurity to define an emitter region;

using a plasma enhanced chemical vapor deposition process forming a second silicon dioxide layer directly on at least the first silicon dioxide layer to thereby form a first passivation layer which includes both the first silicon dioxide layer and the second silicon dioxide layer;

forming a first field plate on the passivation layer, the first field plate extending to electrically contact at least a portion of the emitter region and overlying at least a portion of the epitaxial layer adjacent to the emitter region;

forming a second passivation layer on at least a portion of the first passivation layer and on at least a portion of the first field plate; and

further comprising a step of introducing platinum or gold into the epitaxial layer.

2. The method of claim 1 further including introducing, into a third region spaced apart from the first region and the emitter, opposite conductivity type impurity to define a guard ring surrounding the emitter region.

3. The method of claim 1, wherein the first passivation layer has a thickness 3 microns or less, wherein the second passivation layer comprises polyimide and has a thickness of at least 16 microns.

4. The method of claim 1, wherein the first passivation layer has a thickness 3 microns or less.

5. The method of claim 1, wherein the first passivation layer has a thickness about 0.5 micron to about 3 microns.

6. The method of claim 1, wherein the power semiconductor device comprises a fast recovery diode.

7. The method of claim 1, wherein the power semiconductor device comprises a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).

8. The method of claim 1 further comprising forming a third passivation layer on the second passivation layer.

9. The method of claim 8, wherein the first portion of the first field plate extends along the first lateral direction between the first and second passivation layers, and further including a second portion of a second field plate which extends along the second lateral direction between the second and third passivation layers, wherein the first field plate and the second field plate overlap to prevent foreign particles from penetrating into the interface between the first silicon dioxide layer and the epitaxial layer.

10. The method of claim 9 wherein the power semiconductor device comprises a diode having a blocking voltage of at least about 400 volts.

11. The method of claim 9 wherein the discrete power device comprises a diode, a MOSFET, or an IGBT.

12. The method of claim 9 wherein the second field plate overlaps the first field plate by 2 to 15 microns.

13. The method of claim 1 wherein the first conductivity type is n conductivity type.

14. The method of claim 1 wherein the second passivation layer comprises a polyimide layer.

15. The method of claim 14 wherein the second passivation layer has a thickness of about 3 microns to about 20 microns.