Pixel circuit for global electronic shutter

• US 8,153,947 B2
• Filed: 01/08/2009
• Issued: 04/10/2012
• Est. Priority Date: 01/10/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Barbier, Frédéric, Cazaux, Yvon
• Primary Examiner(s): Epps, Georgia Y
• Assistant Examiner(s): NAPHAS, RENEE D
• Application Number:
  US12/350,677
• Publication Number:
  US 20090200454A1
• Time in Patent Office: 1,188 Days
• Field of Search: 250/208.1, 250/214.1
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/62 Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

An image sensor formed of an array of pixels, each pixel including a photodiode coupled between a first reference voltage and a first switch, the first switch being operable to connect the photodiode to a first node; a capacitor arranged to store a charge accumulated by the photodiode, the capacitor being coupled between a second reference voltage and a second node; a second switch coupled between the first and second nodes, the second switch being operable to connect the capacitor to the first node; and read circuitry coupled for reading the voltage at the second node.

Claims

1. An image sensor comprising an array of pixels, each pixel comprising:

a photodiode coupled between a first reference voltage and a first switch, said first switch operable to connect said photodiode to a first node;

a capacitor arranged to store a charge accumulated by said photodiode, said capacitor being coupled between a second reference voltage and a second node;

a second switch coupled between said first and second nodes, said second switch being operable to connect said capacitor to said first node; and

read circuitry connected to said first node for reading the voltage at said second node, the image sensor further comprising control circuitry arranged to control said first and second switches in each pixel to transfer a charge accumulated by said photodiode to said capacitor at the end of an integration period of said image sensor, and to control, in a row of pixels, the second switch to connect said capacitor to said first node when said row of pixels is to be read, wherein said photodiode is formed in a first P-type well and said second switch comprises a first transistor formed in a second P-type well, said first and second P-type wells having different doping levels, and wherein an N+ type region formed at a junction of said first and second P-type wells serves as said first node.

2. The image sensor of claim 1, wherein, before the end of the integration period, the control circuitry is arranged to control said second switch to couple said first node to said capacitor, and while said first node is coupled to said capacitor by said second switch, to control said first switch to transfer said charge to said capacitor.

3. The image sensor of claim 1, wherein each pixel comprises a light shield formed over said second switch and said first node.

4. The image sensor of claim 1, wherein said read circuitry comprises a sense transistor having its gate node connected to said first node.

5. A digital camera comprising the image sensor of claim 1, a display for displaying images captured by said image sensor and a memory for storing images captured by said image sensor.

6. A mobile telephone comprising the image sensor of claim 1, a display for displaying images captured by said image sensor and a memory for storing images captured by said image sensor.

7. A method of operating an image sensor comprising an array of pixels, each pixel comprising a photodiode, a first node connectable to said photodiode by a first transistor, and a capacitor connectable to said first node by a second transistor, said capacitor arranged to store a charge accumulated by said photodiode, the method comprising:

accumulating charges by said photodiodes during an integration period;

at the end of said integration period, controlling said first and second transistors to transfer said charges to said capacitors; and

reading pixel voltages from a row of said pixels by reading the voltages stored by said capacitors in said row, wherein said photodiode is formed in a first P-type well and said second transistor is formed in a second P-type well, said first and second P-type wells having different doping levels, and wherein an N+ type region formed at a junction of said first and second P-type wells serves as said first node.

8. The method of claim 7, comprising, before the end of said integration period, controlling said second transistor to connect said capacitor to said first node, wherein at the end of said integration period said charge is transferred to said capacitors by controlling said first switch, while the first node is connected to the capacitor, to connect the photodiode to the first node.

9. The method of claim 7, further comprising reading reference voltages from a row of said pixels by resetting the capacitors in said row, and reading the voltage on said capacitors.

10. The method of claim 7, wherein the pixels of said image sensor are controlled to have a common integration period ending at the same time, and wherein rows of said pixels are read sequentially.

11. An image sensor comprising an array of pixels, each pixel comprising:

a photodiode coupled between a first reference voltage and a first transistor, the first transistor configured to connect the photodiode to a first node, the photodiode being formed in a first P-type well;

a capacitor configured to store a charge accumulated by the photodiode, the capacitor being coupled between a second reference voltage and a second node;

a second transistor coupled between the first and second nodes, the second transistor configured to connect the capacitor to the first node, the second transistor being formed in a second P-type well, wherein an N+ type region formed at a junction of the first and second P type wells serves as the first node;

read circuitry coupled to the first node, the read circuitry configured to read a voltage at the second node; and

control circuitry configured to control the first and second transistors to transfer a charge accumulated by the photodiode to the capacitor at an end of an integration period and to connect the capacitor to the first node when the pixel is to be read.

12. An image sensor as defined in claim 11, wherein the first transistor is formed in the first P-type well.

13. An image sensor as defined in claim 11, wherein the first and second P type wells have different doping levels.

14. An image sensor as defined in claim 11, wherein the first and second P type wells are formed in an epitaxial P-type layer.

15. An image sensor as defined in claim 11, further comprising a light shield formed over at least the second P-type well.

16. An image sensor as defined in claim 11, wherein, before the end of the integration period, the control circuitry is configured to control the second transistor to couple the first node to the capacitor, and while the first node is coupled to the capacitor by the second transistor, to control the first transistor to transfer the charge to the capacitor.

17. A method of manufacturing an image sensor comprising an array of pixels, each pixel including a photodiode, a node connected to the photodiode through a first transistor, and a second transistor connectable to a capacitor, comprising:

forming the photodiode and the first transistor in a first P type well;

forming the second transistor in a second P type well; and

forming an N+ type region at a junction between the first and second P type wells, the N+ type region serving as the node.

18. A method as defined in claim 17, wherein the first and second P type wells have different doping levels.

19. A method as defined in claim 17, wherein the first and second P type wells are formed in a epitaxial P type layer.