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Hybrid MRAM array structure and operation

  • US 8,154,004 B2
  • Filed: 11/06/2009
  • Issued: 04/10/2012
  • Est. Priority Date: 06/11/2002
  • Status: Expired due to Fees
First Claim
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1. A phase change memory device, comprising:

  • a first sense line;

    a first plurality of phase change memory bits, each of said first plurality of phase change memory bits being arranged over, and in electrical contact with, said first sense line;

    a second sense line arranged over said first plurality of phase change memory bits;

    a second plurality of phase change memory bits, each of said second plurality of memory bits being arranged over, and in electrical contact with, said second sense line;

    an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of phase change memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of phase change memory bits via said second sense line; and

    a first write only line arranged under said first sense line.

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