Hybrid MRAM array structure and operation

• US 8,154,004 B2
• Filed: 11/06/2009
• Issued: 04/10/2012
• Est. Priority Date: 06/11/2002
• Status: Expired due to Fees

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Micron Technology, Inc.
• Inventors: Seyyedy, Mirmajid, Hush, Glen
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): LULIS, MICHAEL P
• Application Number:
  US12/614,314
• Publication Number:
  US 20100044668A1
• Time in Patent Office: 886 Days
• Field of Search: 257/421, 257/E21.614, 257/E21.665, 257/E27.006, 257/E45.002, 257 1- 5, 257/E21.52, 257/E45.001, 365/148, 365/158, 365/171, 365/173, 438/3, 438/102
• US Class Current: 257/4
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Claims

1. A phase change memory device, comprising:

a first sense line;

a first plurality of phase change memory bits, each of said first plurality of phase change memory bits being arranged over, and in electrical contact with, said first sense line;

a second sense line arranged over said first plurality of phase change memory bits;

a second plurality of phase change memory bits, each of said second plurality of memory bits being arranged over, and in electrical contact with, said second sense line;

an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of phase change memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of phase change memory bits via said second sense line; and

a first write only line arranged under said first sense line.

2. The phase change memory device of claim 1, further comprising:

a substrate;

an access transistor arranged on said substrate, said access transistor having a first active area and a second active area; and

a bit line in electrical contact with said first active area,

wherein said interconnect is in electrical contact with said second active area.

3. The phase change memory device of claim 1, further comprising:

a first plurality of common lines, wherein each of said first plurality of common lines is formed over one of said plurality of first phase change memory bits, and

a second plurality of common lines, wherein each of said second plurality of common lines is formed over one of said plurality of second phase change memory bits.

4. The phase change memory device of claim 3, wherein each of said first plurality of common lines is arranged orthogonally to said first sense line and wherein each of said second plurality of common lines is arranged orthogonally to said second sense line.

5. The phase change memory device of claim 1, further comprising a second write only line arranged under said second sense line.

6. The phase change memory device of claim 1, wherein each of said first plurality of phase change memory bits and each of said second plurality of phase change memory bits is a chalcogenide memory element.

7. A method of fabricating a phase change memory device, comprising:

forming a first sense line;

forming a first plurality of phase change memory bits, each of said first plurality of phase change memory bits being formed over, and in electrical contact with, said first sense line;

forming a second sense line over said first plurality of phase change memory bits;

forming a second plurality of phase change memory bits, each of said second plurality of memory bits being formed over, and in electrical contact with, said second sense line;

forming an interconnect in electrical contact with said first sense line and said second sense line, wherein said interconnect is in electrical contact with said first plurality of phase change memory bits via said first sense line, and wherein said interconnect is in electrical contact with said second plurality of phase change memory bits via said second sense line; and

forming a first write only line under said first sense line.

8. The method of claim 7, further comprising:

providing a substrate;

forming an access transistor on said substrate, said access transistor having a first active area and a second active area; and

providing a bit line in electrical contact with said first active area,

wherein said interconnect is in electrical contact with said second active area.

9. The method of claim 7, wherein the act of forming said first plurality of phase change memory bits comprises:

forming a plurality of first phase change memory storage regions over said first sense line; and

forming a first plurality of common lines;

wherein each of said first plurality of common lines is formed over one of said plurality of first phase change memory storage regions.

10. The method of claim 9, wherein said step of forming said second plurality of phase change memory bits comprises:

forming a plurality of second phase change memory storage regions over said second sense line; and

forming a second plurality of common lines;

wherein each of said second plurality of common lines is formed over one of said plurality of second phase change memory storage regions.

11. The method of claim 10, wherein each of said first plurality of common lines is formed orthogonally to said first sense line and wherein each of said second plurality of common lines is formed orthogonally to said second sense line.

12. The method of claim 7, further comprising forming a second write only line under said second sense line.

13. The method of claim 7, wherein each of said first plurality of phase change memory bits and each of said second plurality of phase change memory bits is a chalcogenide memory element.