Semiconductor device

• US 8,154,073 B2
• Filed: 07/12/2007
• Issued: 04/10/2012
• Est. Priority Date: 07/14/2006
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Aoki, Takaaki, Fujii, Tetsuo, Shiga, Tomofusa
• Primary Examiner(s): Gurley, Lynne
• Assistant Examiner(s): KEARNEY, NAIMA J
• Application Number:
  US11/826,206
• Publication Number:
  US 20080012050A1
• Time in Patent Office: 1,734 Days
• Field of Search: 257/155, 257/330, 257/331, 257/341, 257/342, 257/499, 257/479, 438/179, 438/268, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first conductive type, wherein the substrate has a principal surface and a backside surface, and wherein the substrate includes an inner region and a periphery region;

a vertical type trench gate MOS transistor disposed in a surface portion of the principal surface in the inner region of the substrate;

a Schottky barrier diode disposed in another surface portion of the principal surface in the inner region of the substrate;

a plurality of trenches disposed on the principal surface of the substrate; and

a poly silicon film filled in each trench of the plurality of trenches through an insulation film between the poly silicon film and an inner wall of each trench of the plurality of trenches, wherein

the plurality of trenches have a stripe pattern without crossing each other so that the inner region on the principal surface of the substrate is divided into a plurality of separation regions by the plurality of trenches,

the plurality of separation regions includes a first separation region and a second separation region,

the first separation region includes a first conductive type region and a second conductive type layer disposed on the principal surface of the substrate,

the second conductive type layer provides a channel region of the MOS transistor,

the first conductive type region is disposed on a surface portion of the second conductive type layer, and adjacent to a first trench of the plurality of trenches,

the first conductive type region provides a source of the MOS transistor,

the poly silicon film in the first trench is coupled with a gate wiring of the MOS transistor,

the plurality of trenches further includes a second trench, which is not adjacent to the first conductive type region,

the poly silicon film in the second trench is coupled with a source wiring or the gate wiring of the MOS transistor,

the substrate in the second separation region is exposed on the principal surface in such a manner that the substrate is coupled with the source wiring of the MOS transistor,

the source wiring and the substrate in the second separation region provide a Schottky barrier in the Schottky barrier diode,

the first separation region has a first width between a first two adjacent trenches of the plurality of trenches,

the second separation region has a second width between a second two adjacent trenches,

the plurality of trenches further includes at least two third trenches,

the third trenches are connected between the second two adjacent trenches so that the second two adjacent trenches and the third trenches provide a ladder structure,

the second separation region is divided into a plurality of separation portions each bounded by the at least two third trenches and the second two adjacent trenches, and

the first separation region has a first length, in a direction perpendicular to the second width, the first length being on the principal surface of the substrate,

the plurality of separation portions of the second separation region having a total length, in a direction perpendicular to the second width, the total length being on the principal surface of the substrate,

the first length being longer than the total length.

2. The semiconductor device according to claim 1, wherein

the source wiring is made of a first metallic layer, which covers a surface portion of the principal surface of the substrate, and

the gate wiring is made of a second metallic layer, which surrounds the first metallic layer.

3. The semiconductor device according to claim 1, wherein

the poly silicon film in the second trench is coupled with the source wiring of the MOS transistor.

4. The semiconductor device according to claim 3, further comprising:

a poly silicon layer disposed on the principal surface in the periphery region of the substrate.

5. The semiconductor device according to claim 3, further comprising:

a first metallic layer for providing the source wiring, wherein

the first metallic layer is disposed on the first and second conductive type regions in the first separation region, the poly silicon film in the second trench, and the substrate in the second separation region so that they are commonly coupled with the first metallic layer.

6. The semiconductor device according to claim 1, further comprising:

a poly silicon layer disposed on the principal surface in the periphery region of the substrate.

7. The semiconductor device according to claim 1, wherein

the first and second separation regions are alternately arranged so that the second separation region is sandwiched between the first separation region and another first separation region.

8. The semiconductor device according to claim 1, wherein

the stripe pattern is a linear stripe pattern.

9. The semiconductor device according to claim 8, wherein

the plurality of trenches is in parallel with each other.

10. The semiconductor device according to claim 9, wherein

the first width is equal to the second width.

11. The semiconductor device according to claim 9, wherein

the second width is smaller than the first width.

12. The semiconductor device according to claim 1, wherein

each separation portion has a square shape.

13. The semiconductor device according to claim 1, wherein

a part of the insulation film between the poly silicon film and a bottom of each trench has a thickness, which is larger than a thickness of another part of the insulation film between the poly silicon film and a side wall of each trench.

14. The semiconductor device according to claim 1, wherein

a bottom portion of each trench has a curvature radius, which is larger than a width of a top portion of each trench.

15. The semiconductor device according to claim 1, wherein

the first conductive type is a N conductive type, and the second conductive type is a P conductive type.

16. The semiconductor device according to claim 1, wherein

the semiconductor device provides an inverter circuit, and

the Schottky barrier diode provides a free wheel diode.

17. The semiconductor device according to claim 1, wherein

the semiconductor device is mounted on a vehicle.