Flip chip semiconductor device and process of its manufacture

• US 8,154,105 B2
• Filed: 09/20/2006
• Issued: 04/10/2012
• Est. Priority Date: 09/22/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ma, Ling
• Primary Examiner(s): Zarneke, David
• Application Number:
  US11/524,178
• Publication Number:
  US 20070063316A1
• Time in Patent Office: 2,029 Days
• Field of Search: 257/621, 257/698, 257/E23.011
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor die and method of making it are provided. The die includes a first via extending through the entire thickness of the die and a first via electrode disposed inside the via electrically connecting an electrode at a top surface of the die with another electrode disposed at a bottom surface of the die.

Claims

1. A semiconductor die having a depth of 50 micrometers or less, the semiconductor die comprising:

a first via extending into the body of and through an entire depth of the die and spaced from a first edge of the die; and

a first via electrode disposed inside the via electrically connecting a power electrode disposed on a top surface of the die with another power electrode disposed directly on and extending along an entire coplanar bottom surface of the die, wherein the via is disposed outside the termination region of the die.

2. The die of claim 1, wherein the die is a flip chip MOSFET.

3. The die of claim 1, further comprising at least one additional via identical to the first via and at least one additional via electrode identical to the first via electrode.

4. The die of claim 1, wherein the another power electrode extends along the entire bottom surface of the die.

5. The die of claim 3, wherein a pad electrically connects the first via electrode and the at least one additional via electrode.

6. The die of claim 1, further comprising a source electrode and a gate electrode on the top surface of the die, wherein the power electrode disposed on the top surface of the die comprises a drain electrode.

7. The die of claim 6, further comprising a gate bus extending along edges of the die, wherein the via is disposed between the gate bus and the first edge of the die.

8. The die of claim 1, wherein said first via electrode is electrically connected to the semiconductor die.

9. A vertical conduction power semiconductor device comprising:

a semiconductor die;

a first via extending into and through an entire depth of said die; and

a first via electrode disposed inside said first via electrically connecting a power electrode disposed on a top surface of said die with another power electrode disposed directly on and extending along an entire coplanar bottom surface of said die, wherein said first via is disposed outside a termination region of said die.

10. The semiconductor device of claim 9, wherein said first via electrode is formed of a first material different from a second material used to form said power electrode.

11. The semiconductor device of claim 9, wherein said another power electrode extends along the entire bottom surface of said die.

12. The semiconductor device of claim 9, further comprising a source electrode and a gate electrode on said top surface of said die, wherein said power electrode disposed on said top surface of said die comprises a drain electrode.

13. The semiconductor device of claim 9, wherein said die is a flip chip MOSFET.

14. The semiconductor device of claim 9, further comprising at least one additional via identical to said first via and at least one additional via electrode identical to said first via electrode.

15. The semiconductor device of claim 11, wherein a pad electrically connects said first via electrode and said at least one additional via electrode.