Differential signaling system and flat panel display with the same

• US 8,154,538 B2
• Filed: 01/09/2008
• Issued: 04/10/2012
• Est. Priority Date: 01/11/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Ryu, Jee-youl
• Primary Examiner(s): Eisen, Alexander
• Assistant Examiner(s): Leiby, Christopher E
• Application Number:
  US11/971,408
• Publication Number:
  US 20080211791A1
• Time in Patent Office: 1,553 Days
• Field of Search: 345/55, 345/78, 345/101, 345204-214, 326 82- 87
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching

Abstract

A differential signaling system where a first wire and a second wire are connected to a sending end and a receiving end of a differential signal line. A termination resistor is connected between the first wire and the second wire adjacent to the receiving end. A programmable compensation circuit is connected to the termination resistor in parallel. The programmable compensation circuit includes: a plurality of switches for receiving each bit of an input digital control signal through a gate thereof; a plurality of first capacitors including a first electrode connected to a source electrode of each of the switches, and a second electrode connected to the first wire; and a plurality of second capacitors including a first electrode connected to a drain electrode of each of the switches, and a second electrode connected to the second wire.

Claims

1. A differential signaling system comprising:

a first wire and a second wire connected to a sending end and a receiving end as a differential signal line;

a termination resistor connected between the first wire and the second wire adjacent to the receiving end; and

a programmable compensation circuit connected to the termination resistor in parallel and configured to match an impedance of the first and second wires, wherein the programmable compensation circuit includes;

n switches M1, M2, . . . , Mn for receiving each bit of an input digital control signal through a plurality of gates thereof,

n first capacitors C11, C12, . . . , C1n including a first electrode connected to a source electrode of each of the switches, and a second electrode connected to the first wire, and

n second capacitors C21, C22, . . . , C2n including a first electrode connected to a drain electrode of each of the switches, and a second electrode connected to the second wiring, wherein the resistance of each of the n switches is not included in determining parallel composite impedance of the programmable compensation circuit.

2. The differential signaling system as claimed in claim 1, wherein the number of the switches is equal to the number of digital bits of a control signal for controlling the programmable compensation circuit.

3. The differential signaling system as claimed in claim 1, wherein each switch is a transistor having a minimum distributed gate voltage.

4. The differential signaling system as claimed in claim 1, wherein each of the first n capacitors C11, C12, . . . , C1n;

and each of the second n capacitors C21, C22, . . . , C2n have the same capacitance of (2/n) Cb, and wherein Cb is the effective capacitance value of the programmable compensation circuit.

5. The differential signaling system as claimed in claim 1, wherein the composite impedance of the n first capacitors and the n second capacitors is matched to the total impedance of both the first and second wires.

6. A flat panel display comprising:

a display panel in which a plurality of data wires and gate wires are arranged to intersect each other;

a controller configured to receive an image signal from an exterior source and generate a control signal, output the control signal, and output the image signal through the first and second wires as a differential signal line;

a gate driver configured to receive the control signal from the controller and apply a scan signal to the gate wires; and

a plurality of data driving circuits, each data driving circuit including a programmable compensation circuit connected to a termination resistor in parallel installed between the first and second wires, the programmable compensation circuit configured to automatically match the impedance of the data driving circuit to a differential impedance value of the differential signal line, each of the data driving circuits including a data driver to receive an image signal and/or a control signal from the controller through the first and second wires and applying the image signal to the data wires, wherein the programmable compensation circuit includes;

n switches M1, M2, . . . , Mn to receive each bit of an input digital control signal through a plurality of gates thereof,

n first capacitors C11, C 12, . . . , C1n including a first electrode connected to a source electrode of each of the switches, and a second electrode connected to the first wire, and

n second capacitors C21, C22, . . . , C2n including a first electrode connected to a drain electrode of each of the switches, and a second electrode connected to the second wire, wherein the resistance of each of the n switches is not included in determining parallel composite impedance of the programmable compensation circuit.

7. The flat panel display as claimed in claim 6, wherein the number of the switches is equal to the number of digital bits of the control signal to control the programmable compensation circuit.

8. The flat panel display as claimed in claim 6, wherein each switch is a transistor having a minimum distributed gate voltage.

9. The flat panel display as claimed in claim 6, wherein each of the first n capacitors C11, C12, . . . , C1n;

and each of the second n capacitors C21, C22, . . . , C2n have the same capacitance of (2/n) Cb, and wherein Cb is the effective capacitance value of the programmable compensation circuit.

10. The flat panel display as claimed in claim 6, wherein the composite impedance of the n first capacitors and the n second capacitors is matched to the total impedance of both the first and second wires.

11. A method of matching impedances in a flat display panel comprising a display panel, a plurality of data wires, a controller, a data driver and a plurality of data driving circuits within the data driver each data driving circuit including a programmable compensation circuit connected in parallel to a termination resistor, the method comprising:

receiving an image signal by the controller;

outputting the image signal from the controller through a pair of the plurality of data wires as a differential signal line to the plurality of data driving circuits including the respective programmable compensation circuit connected in parallel to a respective termination resistor;

automatically matching the impedance value of each data driving circuit to correspond to a differential impedance value in the differential signal line through a series of switches and capacitors in the respective programmable compensation circuit; and

transmitting the image signal to the flat display panel, wherein each programmable compensation circuit includes;

n switches M1, M2, . . . , Mn for receiving each bit of the image signal through a plurality of gates thereof, n first capacitors C11, C12, . . . , C1n including a first electrode connected to a source electrode of each of the switches, and a second electrode connected to a first wire of the pair of data wires, and

n second capacitors C21, C22, . . . , C2n including a first electrode connected to a drain electrode of each of the switches, and a second electrode connected to a second wire of the pair of data wires, wherein the resistance of each of the n switches is not included in determining parallel composite impedance of the programmable compensation circuit.

12. The method of matching impedances in the flat display panel of claim 11, comprising a plurality of gate wires and a gate driver, the method further comprising:

generating a control signal in the controller;

receiving the control signal by the gate driver; and

applying a scan signal from the gate driver to the scan wires, wherein the number of switches in each programmable compensation circuit is equal to the number of digital bits in the control signal to control each programmable compensation circuit.

13. The method of matching impedances in the flat display panel of claim 11, wherein each switch is a transistor having a minimum distributed gate voltage.

14. The method of matching impedances in the flat display panel of claim 11, wherein each of the first n capacitors C11, C12, . . . , C1n;

and each of the second n capacitors C21, C22, . . . , C2n have the same capacitance of (2/n) Cb, and wherein Cb is the effective capacitance value of the programmable compensation circuit.

15. The method of matching impedances in the flat display panel of claim 11, wherein the composite impedance of the n first capacitors and the n second capacitors is matched to the total impedance of both the first and second wires.