Method and apparatus for DC restoration using feedback

• US 8,154,664 B2
• Filed: 08/23/2010
• Issued: 04/10/2012
• Est. Priority Date: 08/22/2006
• Status: Active Grant

• Current Assignee: RGB Systems Incorporated
• Original Assignee: RGB Systems Incorporated
• Inventors: Hall, Raymond William, Parreco, Donald E.
• Primary Examiner(s): Kostak, Victor
• Application Number:
  US12/861,316
• Publication Number:
  US 20110069236A1
• Time in Patent Office: 596 Days
• Field of Search: 348/691, 348/692, 348/694, 348/697, 348/725, 348/607, 348/624, 348/222.1, 725/148, 725/149, 345/2.1, 327/307
• US Class Current: 348/692
• CPC Class Codes: H04N 9/72 for reinsertion of DC and slowly varying components of colour signals camera processing pipelines for reinsertion of DC or slowly varying components of colour signals H04N23/87

Abstract

A feedback circuit for restoration of DC in video signals is presented. A sample pulse representing the back porch of an incoming video signal is generated from the horizontal sync signal. The sample pulse triggers a sample and hold circuit to acquire the correct offset voltage in the output signal during this back porch period. The offset voltage feeds back through a summing node upstream of either the circuit causing the offset or an input amplifier thereby restoring the video signal to the desired DC voltage level with respect to ground.

Claims

1. A feedback circuit for compensating for DC offset in an output signal comprising:

a bi-level sync signal detection circuit configured to generate a bi-level sync signal detection pulse upon detection of a bi-level sync signal in said output signal;

a first delay circuit for delaying said bi-level sync signal detection pulse a first period of time;

a tri-level sync signal detection circuit configured to generate a tri-level sync signal detection pulse and disabling said bi-level sync signal detection pulse upon detecting a presence of a tri-level sync signal in said output signal during said first period of time;

a clamp pulse generation circuit for generating a clamp pulse upon receiving said bi-level sync detection pulse or said tri-level sync signal detection pulse;

a sampling circuit configured to sample said output signal during a time period of said clamp pulse to obtain a DC offset value;

a compensation circuit for applying an inverse of said DC offset value to said input signal.

2. The feedback circuit of claim 1 wherein said input signal comprises a video signal.

3. The feedback circuit of claim 1 wherein said sampling circuit comprises a sample-and-hold circuit.

4. The feedback circuit of claim 1 wherein said first delay circuit comprises a plurality of registers.

5. The feedback circuit of claim 1 wherein said clamp pulse generation circuit comprises discrete components.

6. The feedback circuit of claim 1 wherein said claim pulse generation circuit comprises a programmable device.

7. The feedback circuit of claim 6 wherein said programmable device comprises a field programmable gate array.

8. A method for compensating for DC offset in an output signal comprising:

generating a bi-level sync signal detection pulse upon detection of upon detection of a bi-level sync signal in said output signal;

delaying said bi-level sync signal detection pulse a first period of time;

generating a tri-level sync signal detection pulse disabling bi-level sync signal detection pulse upon detecting a presence of a tri-level sync signal in said output signal during said first period of time;

generating a clamp pulse upon receiving said bi-level sync detection pulse or said tri-level sync signal detection pulse;

sampling the output signal during a time period of said clamp pulse to obtain a DC offset value;

subtracting said DC offset value from the input signal.

9. The method of claim 8 wherein said input signal comprises a video signal.

10. The method of claim 9 wherein said time is during a back porch of said video signal.