Delaying a signal communicated from a system to at least one of a plurality of memory circuits

• US 8,154,935 B2
• Filed: 04/28/2010
• Issued: 04/10/2012
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R, Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/769,428
• Publication Number:
  US 20100271888A1
• Time in Patent Office: 713 Days
• Field of Search: 365/194, 365/226
• US Class Current: 365/194
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.

Claims

1. A device comprising:

an interface circuit operable to communicate with a system and with a plurality of physical memory circuits, and to present to the system an emulated memory circuit, the interface circuit including a first component of a first type and a second component of a second different type, wherein the first component is operable to;

receive, from the system, a first signal, wherein the first signal is associated with a first operation to be performed by the emulated memory circuit, the first operation including at least one of a first mode register write operation or a first mode register read operation; and

forward the first signal to the second component after a first delay, wherein the first delay is a function of the first operation associated with the first signal; and

wherein the interface circuit is operable to;

identify at least one physical memory circuit, of the plurality of physical memory circuits, that is not being accessed; and

perform a power-saving operation on the identified at least one physical memory circuit that is not being accessed.

2. The device of claim 1, wherein the interface circuit is operable to:

receive, from the system, a second signal, wherein the second signal is associated with a second operation to be performed by the emulated memory circuit, the second operation including at least one of a write operation, a read operation, a refresh operation, a second mode register write operation, a second mode register read operation, an activate operation, or a precharge operation; and

forward one or more copies of the second signal to one or more physical memory circuits of the plurality of physical memory circuits, respectively.

3. The device of claim 2, wherein the second signal is an address, control, or data signal.

4. The device of claim 1, wherein the first signal is a control signal.

5. The device of claim 1, wherein the second component is operable to:

receive, from the system, a data signal sent to the emulated memory circuit; and

forward the data signal to at least one physical memory circuit of the plurality of physical memory circuits.

6. The device of claim 5, wherein the second component is operable to forward the data signal to the at least one physical memory circuit after a second delay.

7. The device of claim 6, wherein the second delay is not an integer number of clock cycles.

8. The device of claim 1, wherein the first delay is not an integer number of clock cycles.

9. The device of claim 1, wherein the first delay is a multiple clock cycle delay.

10. The device of claim 1, wherein the first component of the first type is a register and the second component of the second type is a buffer.

11. The device of claim 10, wherein the register is operable to control the buffer.

12. The device of claim 1, wherein the interface circuit is operable to perform the power-saving operation by placing the identified at least one physical memory circuit in a power down mode.

13. The device of claim 12, wherein the power down mode is a precharge power down mode.

14. The device of claim 12, wherein the interface circuit is operable to place the identified at least one physical memory circuit in a power down mode by controlling a clock enable input of the identified at least one physical memory circuit.

15. The device of claim 1, wherein the interface circuit is operable to identify the at least one physical memory circuit that is not being accessed based on how many pages are open in one or more physical memory circuits of the plurality of physical memory circuits.

16. The device of claim 1, wherein the interface circuit is operable to present the emulated memory circuit as having a memory capacity that is greater than a memory capacity of each physical memory circuit of the plurality of physical memory circuits.

17. The device of claim 1, further comprising a dual in-line memory module (DIMM), wherein the interface circuit is coupled to the DIMM.

18. The device of claim 1, wherein the interface circuit is further operable to receive a second signal from at least one physical memory circuit of the plurality of physical memory circuits and communicate the second signal to the system after a second delay.

19. The device of claim 1, wherein the first component is operable to forward the first signal to the second component after the first delay such that the first delay is transparent to the system.

20. A device comprising:

an interface circuit operable to communicate with a system and with a plurality of physical memory circuits, and to present to the system an emulated memory circuit, the interface circuit including a first component of a first type and a second component of a second different type, wherein the first component is operable to;

receive, from the system, a first signal, wherein the first signal is associated with a first operation to be performed by the emulated memory circuit, the first operation including at least on of a first mode register write operation or a first mode register read operation; and

forward the first signal to the second component after a first delay, wherein the first delay is a function of the first operation associated with the first signal,

wherein the interface circuit is further operable to;

receive, from the system, a second signal, wherein the second signal is associated with a second operation to be performed by the emulated memory circuit, the second operation including at least one of a write operation, a read operation, a refresh operation, a second mode register operation, an activate operation, or a precharge operation; and

forward one or more copies of the second signal to one or more physical memory circuits of the plurality of physical memory circuits, respectively.

21. The device of claim 20, wherein the second signal is an address, control, or data signal.

22. The device of claim 20, wherein the first signal is a control signal.

23. The device of claim 20, wherein the second component is operable to:

receive, from the system, a data signal sent to the emulated memory circuit; and

forward the data signal to at least one physical memory circuit of the plurality of physical memory circuits.

24. The device of claim 23, wherein the second component is operable to forward the data signal to the at least one physical memory circuit after a second delay.

25. The device of claim 24, wherein the second delay is not an integer number of clock cycles.

26. The device of claim 20, wherein the first delay is not an integer number of clock cycles.

27. The device of claim 20, wherein the first delay is a multiple clock cycle delay.

28. The device of claim 20, wherein the first component of the first type is a register and the second component of the second type is a buffer.

29. The device of claim 28, wherein the register is operable to control the buffer.

30. The device of claim 24, wherein the interface circuit is operable to:

identify at least one physical memory circuit, of the plurality of physical memory circuits, that is not being accessed; and

perform a power-saving operation on the identified at least one physical memory circuit that is not being accessed by placing the identified at least one physical memory circuit in a power down mode.

31. The device of claim 30, wherein the power down mode is a precharge power down mode.

32. The device of claim 30, wherein the interface circuit is operable to place the identified at least one physical memory circuit in a power down mode by controlling a clock enable input of the identified at least one physical memory circuit.

33. The device of claim 30, wherein the interface circuit is operable to identify the at least one physical memory circuit that is not being accessed based on how many pages are open in one or more physical memory circuits of the plurality of physical memory circuits.

34. The device of claim 20, wherein the interface circuit is operable to present the emulated memory circuit as having a memory capacity that is greater than a memory capacity of each physical memory circuit of the plurality of physical memory circuits.

35. The device of claim 20, further comprising a dual in-line memory module (DIMM), wherein the interface circuit is coupled to the DIMM.

36. The device of claim 20, wherein the interface circuit is further operable to receive a second signal from at least one physical memory circuit of the plurality of physical memory circuits and communicate the second signal to the system after a second delay.

37. The device of claim 20, wherein the first component is operable to forward the first signal to the second component after the first delay such that the first delay is transparent to the system.