Multi-column addressing mode memory system including an integrated circuit memory device
First Claim
1. An integrated circuit memory device, comprising:
- at least one storage array having storage cells arranged in plural rows and plural columns;
a row decoder to select a row of storage cells within the at least one storage array;
an interface to couple the integrated circuit memory device with an external interconnect; and
circuitry to concurrently convey data between the interface and a subset of the selected row corresponding to at least two selectively non-contiguous column addresses.
0 Assignments
0 Petitions
Accused Products
Abstract
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
114 Citations
39 Claims
-
1. An integrated circuit memory device, comprising:
-
at least one storage array having storage cells arranged in plural rows and plural columns; a row decoder to select a row of storage cells within the at least one storage array; an interface to couple the integrated circuit memory device with an external interconnect; and circuitry to concurrently convey data between the interface and a subset of the selected row corresponding to at least two selectively non-contiguous column addresses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. An integrated circuit memory device, comprising:
-
at least one storage array having storage cells arranged in plural rows and plural columns; a row decoder to select a row of storage cells within the at least one storage array; an interface to couple the integrated circuit memory device with an external interconnect; and circuitry to generate multiple column addresses for accessing respective, selectively non-contiguous portions of the selected row during a single column cycle time interval and to exchange data via the interface with the external interconnect. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
-
-
38. An integrated circuit memory device, comprising:
-
first, second, third and fourth storage arrays each having storage cells arranged in plural rows and plural columns; a first row decoder to select a row of storage cells within the first array and the second array; a second row decoder to select a row of storage cells within the third array and the fourth array; an interface to couple the first and third storage arrays with a first portion of an external interconnect and to couple the third and fourth storage arrays with a second portion of an external interconnect; circuitry to concurrently convey data between first and second columns within the first and second storage arrays, respectively, and the interface, and to concurrently convey data between third and fourth columns within the third and fourth storage arrays, respectively, and the interface, so as to concurrently exchange data between at least two columns for each selected row and the interface where the column addresses for the first and second columns are selectively non-contiguous, and where column addresses for the third and fourth columns are selectively non-contiguous. - View Dependent Claims (39)
-
Specification