Direct slave-to-slave data transfer on a master-slave bus

• US 8,156,274 B2
• Filed: 02/02/2009
• Issued: 04/10/2012
• Est. Priority Date: 02/02/2009
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Kapelner, Jordan S.
• Primary Examiner(s): Myers, Paul R
• Assistant Examiner(s): DALEY, CHRISTOPHER ANTHONY
• Application Number:
  US12/364,175
• Publication Number:
  US 20100199007A1
• Time in Patent Office: 1,163 Days
• Field of Search: 710/110, 710/36, 713/2, 711/103
• US Class Current: 710/110
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

A method and system for transferring data between two slave devices. A system includes a master device and first and second slave devices coupled to the master device by a peripheral bus. The master device is configured to configure the first slave device as a source for a read operation, configure the second slave device as a target for a write operation, provide a clock signal to both the first slave device and the second slave device, and initiate a read operation of the first slave device. Initiation of the read operation causes the first slave device to provide data onto the peripheral bus. Responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device. The master device is configured to ignore the data provided on the peripheral bus by the first slave device.

Claims

1. An electronic system comprising:

a master device;

a first slave device coupled to the master device by a peripheral bus; and

a second slave device coupled to the master device and the first slave device by the peripheral bus;

wherein the master device is configured to;

configure the first slave device as a source for a read operation, wherein, in configuring the first slave device, the master device is configured to provide a beginning read address to the first slave device;

configure the second slave device as a target for a write operation, wherein, in configuring the second slave device, the master device is configured to provide a beginning write address to the second slave device;

provide a clock signal to both the first slave device and the second slave device; and

initiate a read operation of the first slave device, wherein initiating a read operation causes the first slave device to provide data onto the peripheral bus;

wherein, responsive to the master device initiating the read operation, the second slave device is configured to receive the data provided on the peripheral bus by the first slave device, wherein the first slave device is configured to automatically increment read addresses and wherein the second slave device is configured to automatically increment write addresses; and

wherein the master device is configured to ignore the data provided on the peripheral bus by the first slave device.

2. The electronic system as recited in claim 1,

wherein the second slave device includes an output pin that is separately enabled from the input pin;

wherein the second slave device is configured to inhibit its output pin during the read operation.

3. The electronic system as recited in claim 1, wherein the first slave device and the second slave device each include a bi-directional data pin, and wherein the bi-directional data pin of the first slave device is coupled to the bi-directional pin of the second slave device by a bi-directional data line on the bus.

4. The electronic system as recited in claim 1, wherein, during transfer of data from the first slave device to the second slave device, the master device and the second slave device operate in an input mode, and wherein the first slave device operates in an output mode.

5. The electronic system as recited in claim 1, wherein the peripheral bus is a serial peripheral interface (SPI) bus.

6. The electronic system as recited in claim 1, wherein the first slave device is a flash memory device and wherein the second slave device is a display device.

7. The electronic system as recited in claim 1, wherein the master device is a keyboard controller.

8. A method for performing data transfer in a system comprising a master device, a first slave device, and a second slave device coupled together by a peripheral bus, the method comprising:

configuring, by the master device, the first slave device as a source of data for a read operation;

configuring, by the master device, the second slave device as a target for performing a write operation;

providing a clock signal to the first slave device and the second slave device, wherein the clock signal is provided by the master device;

initiating, by the master device, a read operation of the first slave device;

the first slave device providing data onto the peripheral bus in response to the read operation initiated by the master device;

the second slave device receiving the data provided on the peripheral bus by the first slave device responsive to the master device initiating the read operation;

the first slave device automatically incrementing read addresses;

the second slave device automatically incrementing write addresses; and

wherein the master device is configured to ignore the data provided on the peripheral bus by the first slave device.

9. A method performed by a master device for performing data transfer in a system comprising the master device, a first slave device, and a second slave device coupled together by a peripheral bus, the method comprising:

configuring the first slave device as a source of data for a read operation, wherein said configuring the first slave device comprises providing a beginning read address to the first slave device and configuring the first slave device to automatically increment read addresses;

configuring the second slave device as a target for performing a write operation, wherein said configuring the second slave device comprises providing a beginning write address to the second slave device and configuring the second slave device to automatically increment write addresses;

providing a clock signal to the first slave device and the second slave device, wherein the clock signal is provided by the master device;

initiating a read operation of the first slave device, wherein the read operation causes the first slave device to provide data onto the peripheral bus;

wherein, responsive to the master device initiating the read operation, the second slave device receives the data provided on the peripheral bus by the first slave device; and

wherein the master device is configured to ignore the data provided on the peripheral bus by the first slave device.

10. The method as recited in claim 9,

wherein the peripheral bus is a serial peripheral interface (SPI) bus;

and

wherein the master device is a keyboard controller.

11. A master device which is operable to configure a data transfer between a first slave device and a second slave device, comprising:

a bus interface for coupling to a peripheral bus, wherein the first slave device and the second slave device are coupled to the peripheral bus;

a processor;

a memory medium coupled to the processor which stores program instructions executable by the processor to;

configure the first slave device as a source for a read operation, wherein, in configuring the first slave device, the master device is configured to provide a beginning read address to the first slave device, and wherein, in configuring the first slave device, the master device is operable to configure the first slave device to automatically increment read addresses;

configure the second slave device as a target for a write operation wherein, in configuring the second slave device, the master device is configured to provide a beginning write address to the second slave device, and wherein, in configuring the second slave device, the master device is operable to configure the second slave device to automatically increment write addresses;

provide a clock signal to both the first slave device and the second slave device; and

initiate a read operation of the first slave device, wherein initiation of the read operation causes the first slave device to provide data onto the peripheral bus;

wherein configuration of the second slave device causes the second slave device to be configured to receive the data provided on the peripheral bus by the first slave device responsive to the master device initiating the read operation; and

wherein the master device is configured to ignore the data provided on the peripheral bus by the first slave device.

12. A computer-readable memory medium comprised on a master device, wherein the master device couples through a peripheral bus to a first slave device and a second slave device, wherein the computer-readable memory medium stores program instructions executable by a processor to:

configure the first slave device as a source for a read operation, wherein, in configuring the first slave device, the program instructions are executable to provide a beginning read address to the first slave device, and wherein, in configuring the first slave device, the program instructions are executable to configure the first slave device to automatically increment read addresses;

configure the second slave device as a target for a write operation, wherein, in configuring the second slave device, the program instructions are executable to provide a beginning write address to the second slave device, wherein, in configuring the second slave device, the program instructions are executable to configure the second slave device to automatically increment write addresses;

provide a clock signal to both the first slave device and the second slave device; and

initiate a read operation of the first slave device, wherein initiation of the read operation causes the first slave device to provide data onto the peripheral bus intended for the master device;

wherein configuration of the second slave device causes the second slave device to be configured to receive the data provided on the peripheral bus by the first slave device responsive to the master device initiating the read operation; and

wherein the master device is configured to ignore the data provided on the peripheral bus by the first slave device.