Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set

• US 8,156,307 B2
• Filed: 08/20/2007
• Issued: 04/10/2012
• Est. Priority Date: 08/20/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Wallach, Steven J., Brewer, Tony
• Primary Examiner(s): Dudek, Jr., Edward
• Assistant Examiner(s): VERDERAMO III, RALPH
• Application Number:
  US11/841,406
• Publication Number:
  US 20090055596A1
• Time in Patent Office: 1,695 Days
• Field of Search: None
• US Class Current: 711/203
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/24 Loading of the microprogram
• CPC Class Codes: G06F 9/3881 Arrangements for communication of instructions and data
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor'"'"'s instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co-processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.

Claims

1. A system comprising:

a manufactured processor element having a fixed instruction set that defines instructions that the processor element can execute and that is not modifiable by a consumer, and a reconfigurable co-processor, wherein said processor element is not designed to natively offload to said reconfigurable co-processor instructions of an executable file that is running on the processor element;

said reconfigurable co-processor comprising reconfigurable logic that is reconfigurable to have an entirety of any one of a plurality of predefined extended instruction sets for extending the fixed instruction set of the processor element for processing instructions of an executable file, each of said plurality of predefined extended instruction sets defining a plurality of instructions that the reconfigurable co-processor can execute, wherein said plurality of instructions comprise extended instructions that are not natively defined by the fixed instruction set of the processor element, and wherein the extended instruction sets are not embedded within said executable file;

said processor element comprises a first instruction decode logic that is operable to decode instructions of the executable file that are defined by the processor element'"'"'s fixed instruction set for execution by the processor element; and

wherein the reconfigurable co-processor comprises a second instruction decode logic that is operable to decode instructions of the executable file that are defined by the extended instruction set that the reconfigurable co-processor is configured to have for execution by the reconfigurable co-processor;

said reconfigurable co-processor sharing a common virtual and physical address space with said processor element; and

a global shared, cache coherent physical address space, whereby the processor element comprises a physical memory and a cache, and whereby the co-processor comprises a physical memory and a cache, and wherein data contained in the processor element'"'"'s cache and the co-processor'"'"'s cache are maintained in a cache coherent state.

2. The system of claim 1 wherein said cache coherency is maintained via hardware.

3. The system of claim 1 wherein said fixed instruction set of said processor element is an x86 instruction set.

4. The system of claim 1 further comprising:

persistent data storage for storing said plurality of predefined extended instruction sets, each said predefined extended instruction set optimized for processing a corresponding class of operations.

5. The system of claim 4 further comprising:

means for selecting which of said stored extended instruction sets is to be used by said co-processor as its instruction set.

6. The system of claim 5 wherein said selecting means is enabled by said executable file executing on said system, wherein said co-processor processes a portion of an instruction stream of said executable file using the selected extended instruction set.

7. The system of claim 6 wherein the extended instruction set selected for use by said co-processor as its instruction set is not included in said executable file.

8. The system of claim 1 wherein said co-processor'"'"'s instruction set is changeable in accordance with said executable file currently being run on said system, said executable file running partially on said processor element and partially on said co-processor.

9. The system of claim 8 wherein said instruction set of said co-processor is changeable within said co-processor dependent upon an identity of at least one of said plurality of predefined extended instruction sets by said currently running executable file.

10. The system of claim 8 wherein a portion of said executable file executes on said processor element concurrent with a portion of said executable file executing on said co-processor.

11. The system of claim 1 further comprising:

said first processor element and said co-processor using a common virtual memory format.

12. The system of claim 11 further comprising:

said processor element comprising a first translation table for translating virtual addresses to physical addresses;

said co-processor comprising a second translation table for translating virtual addresses to physical addresses; and

wherein said first translation table and said second translation table have common translation entries.

13. The system of claim 1 further comprising:

said processor element'"'"'s physical memory comprising a first main memory;

said co-processor'"'"'s physical memory comprising a second main memory; and

wherein said first main memory and said second main memory are in a common global physical memory space.

14. The system of claim 13 further comprising:

a designated portion of at least one of said first main memory and said second main memory to which the processor element stores instructions of the executable file for processing by said co-processor.

15. The system of claim 1 wherein a first portion of said executable file executes on said processor element and a second portion of said executable file executes on said co-processor.

16. The system of claim 15 wherein said first portion and said second portion of said executable file execute concurrently.

17. The system of claim 1 wherein said processor element is implemented on a first integrated circuit, and said reconfigurable co-processor is not implemented on said first integrated circuit.

18. A method comprising:

initiating an executable file for processing instructions of the executable file by a system, wherein the system comprises at least one host processor having a first instruction decode logic and an instruction set that defines instructions that the first instruction decode logic can decode for execution by the at least one host processor, and the system further comprising at least one dynamically reconfigurable co-processor having a second instruction decode logic, wherein said at least one host processor comprises a manufactured host processor haying a fixed instruction set that is not modifiable by a consumer, and wherein said at least one dynamically reconfigurable co-processor is not implemented on a same integrated circuit as said manufactured host processor;

determining one of a plurality of fixed instruction set images to load to said at least one dynamically reconfigurable co-processor for processing a portion of the instructions of the executable file, wherein the determined instruction set image defines an instruction set having a plurality of instructions that the second instruction decode logic can decode for execution by the dynamically reconfigurable co-processor, and wherein said plurality of instructions of the determined instruction set image comprise extended instructions that are not natively defined by the instruction set of the at least one host processor, and wherein the determined instruction set image is not embedded within the executable file;

when determined that the determined instruction set image is not present on the dynamically reconfigurable co-processor, loading the determined instruction set image in its entirety from persistent storage to the dynamically reconfigurable co-processor; and

processing, by the system, the instructions of the executable file, wherein a first portion of the instructions of the executable file that are defined by the instruction set of the at least one host processor is decoded by the first instruction decode logic and processed by the at least one host processor and a second portion of the instructions of the executable file comprising one or more of said extended instructions defined by the determined instruction set image is decoded by the second instruction decode logic and processed by the at least one dynamically reconfigurable co-processor, wherein said processing of said second portion of the instructions by the at least one dynamically reconfigurable co-processor does not require determining on an instruction-by-instruction basis whether the dynamically reconfigurable co-processor is configured with an instruction set that defines said instructions of said second portion, and wherein said at least one host processor is not designed to natively offload said second portion of instructions in said executable file executing on said at least one host processor to said at least one dynamically reconfigurable co-processor for processing.

19. The method of claim 18 further comprising:

determining whether the dynamically reconfigurable co-processor is configured to possess said determined instruction set image.

20. The method of claim 18 wherein determining the instruction set image to load to said at least one dynamically reconfigurable co-processor comprises:

determining the instruction set image from information included in the executable file.

21. The method of claim 20 wherein the information included in the executable file identifies one of the plurality of fixed instruction set images.

22. The method of claim 21 wherein each of said plurality of fixed instruction set images is optimized for processing a corresponding class of operations.

23. The method of claim 22 wherein said plurality of fixed instruction set images comprise at least one of the following:

a vector instruction set designed for efficiently processing 64-bit floating point operations;

a vector instruction set designed for efficiently processing 32-bit floating point operations;

an instruction set designed for efficiently processing cryptography-related operations;

an instruction set designed for efficiently performing operations for manipulating bit or byte strings;

an instruction set designed for efficiently performing computer-aided simulation operations; and

an instruction set designed for efficiently performing image processing operations.

24. The method of claim 18 wherein said instruction set of the at least one host processor is an x86 instruction set.

25. The method of claim 18 further comprising:

maintaining cache coherency between said at least one host processor and said at least one dynamically reconfigurable co-processor.

26. The method of claim 18 wherein said loading comprises:

loading the determined instruction set image to the co-processor before beginning execution of any of said instructions of the executable file by said at least one host processor and said at least one dynamically reconfigurable co-processor.