L2 ECC implementation

• US 8,156,404 B1
• Filed: 08/29/2008
• Issued: 04/10/2012
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Glasco, David B., Holmqvist, Peter B., Lynch, George R., Marchand, Patrick R., Mehra, Karan, Roberts, James
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Leibovich, Yair
• Application Number:
  US12/202,161
• Time in Patent Office: 1,320 Days
• Field of Search: 714/766, 711/122
• US Class Current: 714/766
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.

Claims

1. A method for implementing error code correction (ECC) protection with respect to a read operation to an external memory via an intermediary cache, the method comprising:

issuing a read command to the external memory to retrieve a word of data comprised of a plurality of bytes;

reading the plurality of bytes returned from the external memory in response to the read command;

generating one or more ECC check bits for the plurality of bytes; and

storing the one or more ECC check bits in the intermediary cache instead of storing a byte enable for each byte in the plurality of bytes.

2. The method of claim 1, further comprising the step of setting an indicator bit indicating that the intermediary cache includes the one or more ECC check bits instead of the byte enable for each byte in the plurality of bytes.

3. The method of claim 2, further comprising the step of storing the indicator bit in the intermediary cache.

4. The method of claim 1, wherein the one or more ECC check bits are stored within a byte enable storage element within the intermediary cache, and further comprising the step of storing the plurality of bytes in a data storage element within the intermediary cache.

5. The method of claim 1, wherein the one or more ECC check bits are generated for the whole word of data.

6. The method of claim 1, wherein the word of data is partitioned into two or more pieces, and the one or more ECC check bits are generated separately for each of the two or more pieces.

7. A non transitory computer-readable medium including instructions that, when executed by a processor, cause the processor to implement error code correction (ECC) protection with respect to a read operation to an external memory via an intermediary cache, by performing the steps of:

issuing a read command to the external memory to retrieve a word of data comprised of a plurality of bytes;

reading the plurality of bytes returned from the external memory in response to the read command;

generating one or more ECC check bits for the plurality of bytes; and

storing the one or more ECC check bits in the intermediary cache instead of storing a byte enable for each byte in the plurality of bytes.

8. The computer-readable medium of claim 7, further comprising the step of setting an indicator bit indicating that the intermediary cache includes the one or more ECC check bits instead of the byte enable for each byte in the plurality of bytes.

9. The computer-readable medium of claim 8, further comprising the step of storing the indicator bit in the intermediary cache.

10. The computer-readable medium of claim 7, wherein the one or more ECC check bits are stored within a byte enable storage element within the intermediary cache, and further comprising the step of storing the plurality of bytes in a data storage element within the intermediary cache.

11. The computer-readable medium of claim 7, wherein the one or more ECC check bits are generated for the whole word of data.

12. The computer-readable medium of claim 7, wherein the word of data is partitioned into two or more pieces, and the one or more ECC check bits are generated separately for each of the two or more pieces.

13. A computer system configured to implement error code correction (ECC) protection with respect to a read operation to an external memory via an intermediary cache, the computer system comprising:

a central processing unit (CPU);

system memory coupled to the CPU; and

a parallel processing subsystem coupled to the CPU and to the external memory and including the intermediary cache, wherein the intermediary cache includes;

a data storage element

a byte enable storage element, and

control logic configured to;

issue a read command to the external memory to retrieve a word of data comprised of a plurality of bytes,

read the plurality of bytes returned from the external memory in response to the read command,

generate one or more ECC check bits for the plurality of bytes, and

store the one or more ECC check bits in the byte enable storage element instead of storing a byte enable for each byte in the plurality of bytes.

14. The computer system of claim 13, wherein the control logic is further configured to set an indicator bit indicating that the intermediary cache includes the one or more ECC check bits instead of the byte enable for each byte in the plurality of bytes.

15. The computer system of claim 14, wherein the control logic is further configured to store the indicator bit in the intermediary cache.

16. The computer system of claim 13, wherein the control logic is further configured to store the plurality of bytes in the data storage element.

17. The computer system of claim 13, wherein the one or more ECC check bits are generated for the whole word of data.

18. The computer system of claim 13, wherein the word of data is partitioned into two or more pieces, and the one or more ECC check bits are generated separately for each of the two or more pieces.