Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing

• US 8,156,463 B1
• Filed: 10/29/2007
• Issued: 04/10/2012
• Est. Priority Date: 02/09/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Fung, Ryan, Betz, Vaughn, Chow, William
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US11/978,356
• Time in Patent Office: 1,625 Days
• Field of Search: 716 4- 6, 716110-114
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay budgets.

Claims

1. A method for designing a system on a target device, comprising:

identifying path-level hold time associated with the system, wherein the path-level hold time limits a delay from a first location on a path in the system to a second location on the path in the system to be greater than a predetermined value; and

selecting routing resources on the target device to increase delay for connections in the path in response to the path-level hold time by determining a minimum delay for the connections computed from lower delay limits of routed connections in response to available routing paths on the target device for the connections in response to short-path timing constraints, wherein the selecting is further responsive to the minimum delay, and, wherein at least one of the identifying and selecting is performed by a processor.

2. The method of claim 1, wherein the routing resources are programmable logic device routing resources.

3. The method of claim 1, wherein the lower delay limits of the routed connections are computed further in response to an initial selection of routing resources that reduces connection delays and ignores shorted signals.

4. The method of claim 1, wherein determining the minimum delay computing initial estimates of final routed delay.

5. The method of claim 1, wherein determining the minimum delay for the connections comprises finding a set of connection delays that satisfy the short-path timing constraints.

6. The method of claim 1, wherein determining the minimum delay for the connections comprises allocating short-path slack.

7. The method of claim 1, wherein the path-level hold time comprises short-path timing constraints.

8. An non-transitory computer-readable medium having stored thereon sequences of instructions, the sequences of instructions including instructions which, when executed by a processor, causes the processor to execute a method comprising:

identifying path-level hold time associated with a system that limit a delay from a first location on a path in the system to a second location on the path in the system to be greater than a predetermined value; and

selecting routing resources on a target device to increase delay for connections in the path in response to the path-level hold time by determining a minimum delay for the connections computed from lower delay limits of routed connections in response to available routing paths on the target device for the connections in response to short-path timing constraints, wherein the selecting is further responsive to the minimum delay, and, wherein one of the identifying and selecting is performed by a processor.

9. The machine-readable medium of claim 8, wherein the routing resources are programmable logic device routing resources.

10. The machine-readable medium of claim 8, wherein the path-level hold time comprises is short-path timing constraints.

11. A system designer, comprising:

a slack allocation unit operable to identify a path-level hold time associated with a system that limits a delay from a first location on a path in the system to a second location on the path in the system to be greater than a predetermined value, and operable to determine a minimum delay for connections in the path based on the path-level hold time and lower delay limits of routed connections in response to available routing paths; and

a routing unit operable to select routing resources on a target device to increase delay for connections in the path in response to the path-level hold time, wherein selecting the routing resources is responsive to the minimum delay.

12. The system designer of claim 11, wherein the slack allocation unit comprises a timing analysis unit operable to generates short-path slack values for the connections based on connection delays and the path-level hold time.

13. The system designer of claim 11, wherein the slack allocation unit comprises a delay adjustment unit operable to modify a set of temporary connection delays to satisfy the path-level hold time.

14. The system designer of claim 11, wherein the slack allocation unit comprises a delay adjustment unit operable to modify a set of temporary connection delays to allocate short-path slack.

15. The system designer of claim 11, wherein the hold time comprises short-path timing constraints.

16. The system designer of claim 11, wherein the routing resources are programmable logic device routing resources.